Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a stacked gate structure positioned on the substrate; first spacers attached on two sides of the stacked gate structure; and second spacers attached on two sides of the first spacers; wherein the first spacers comprise graphene.

Abstract: A light emitting device includes: a light emitting element having an emission peak wavelength in a range of 430 nm to 470 nm; and a fluorescent member including a fluorescent material that is excited by light from the light emitting element for light emission, wherein a mixture of light from the light emitting element and light from the fluorescent material has a correlated color temperature in a range of 1500 K to 11000 K, as measured according to JIS Z8725, the color deviation duv that is a deviation from the black body radiation track on the CIE1931 chromaticity diagram of the mixture of light and is measured according to JIS Z8725 falls within a range of more than 0 to 0.

Abstract: A semiconductor device package includes a main substrate, at least one thin film transistor (TFT) module, at least one first electronic component, at least one encapsulant and a plurality of light emitting devices. The main substrate has a first surface and a second surface opposite to the first surface. The thin film transistor (TFT) module is disposed adjacent to and electrically connected to the first surface of the main substrate. The first electronic component is disposed adjacent to and electrically connected to the first surface of the main substrate. The encapsulant covers the at least one thin film transistor (TFT) module and the at least one first electronic component. The light emitting devices are electrically connected to the at least one thin film transistor (TFT) module.

Abstract: A semiconductor light emitting device includes a light extraction layer having a light extraction surface. Multiple cone-shaped parts formed in an array are provided on the light extraction surface of the semiconductor light emitting device. A proportion of an area occupied by the multiple cone-shaped parts per a unit area of the light extraction surface is not less than 65% and not more than 95% in a plan view of the light extraction surface, and an aspect ratio h/p defined as a proportion of a height h of the cone-shaped part relative to a distance p between apexes of adjacent cone-shaped parts is not less than 0.3 and not more than 1.0.

Abstract: A semiconductor device includes a semiconductor substrate, a first current-carrying electrode, a second current-carrying electrode, a first control electrode disposed between the first current-carrying electrode and the second current-carrying electrode, a third current-carrying electrode electrically coupled to the first current-carrying electrode, and a fourth current-carrying electrode adjacent the third current-carrying electrode. The third current-carrying electrode and the fourth current-carrying electrode are configured to support current flow from the third current-carrying electrode to the fourth current-carrying electrode parallel to a second direction. The fourth current-carrying element is electrically coupled to the second current-carrying electrode and a second control electrode. The second control electrode is electrically coupled to the first control electrode.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a processor, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of dynamic random-access memory (DRAM) cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

Abstract: A method of manufacturing a light-emitting device includes: arranging a plurality of light-emitting elements each having an upper surface; disposing a first reflective member between the plurality of light-emitting elements such that the upper surface of each of the plurality of light-emitting elements are exposed and such that lateral surfaces of the light-emitting elements are covered with the first reflective member; disposing a light-transmissive member over the upper surface of each of the plurality of light-emitting elements and the first reflective member; forming a plurality of grooves surrounding one or two or more light-emitting elements by removing a portion of the light-transmissive member and a portion of the first reflective member; disposing a second reflective member to fill the plurality of grooves; and cutting the second reflective member to perform singulation.

Abstract: Provided is a light-emitting device including a substrate, a light-emitting pattern provided on the substrate, a first reflection film provided between the light-emitting pattern and the substrate, a second reflection film provided on a side surface of the light-emitting pattern, and a passivation film provided between the light-emitting pattern and the second reflection film, wherein the second reflection film is electrically connected to the light-emitting pattern, and a portion of light generated from the light-emitting pattern is emitted through an upper surface of the light-emitting pattern after being reflected by at least one of the first reflection film and the second reflection film.

Abstract: A light-emitting module and a light-emitting diode are provided. The light-emitting diode includes an epitaxial light-emitting structure to generate a light beam with a broadband blue spectrum. A spectrum waveform of the broadband blue spectrum has a full width at half maximum (FWHM) larger than or equal to 30 nm. The spectrum waveform has a plurality of peak inflection points, and a difference between two wavelength values to which any two adjacent ones of the peak inflection points respectively correspond is less than or equal to 18 nm.

Abstract: A semiconductor device includes an electric circuit configured to include, a transistor, a first pad coupled to a gate or a drain of the transistor, a second pad coupled to the gate or the drain of the transistor, a first wiring that extends from the gate or the drain of the transistor to the first pad, and a second wiring that diverges from the first wiring and extends to the second pad, and a redistribution layer formed over the electric circuit and configured to include a first redistribution coupled to the first pad, and a second redistribution coupled to the second pad to constitute a stub.

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

Abstract: A semiconductor device includes a semiconductor part of a first conductivity type, a trench being provided in the semiconductor part at a front surface side; a first electrode provided on a back surface of the semiconductor part; a second electrode provided on the front surface of the semiconductor part; a first semiconductor layer of a second conductivity type provided inside the trench; and a insulating film electrically isolating the first semiconductor layer from the semiconductor part. The second electrode is electrically connected to the semiconductor part and the first semiconductor layer. The second electrode contacts the semiconductor part with a rectification property.

Abstract: A merged-PN-Schottky, MPS, diode includes an N substrate, an N-drift layer, a P-doped region in the drift layer, an ohmic contact on the P-doped region, a plurality of cells within the P-doped region and being portions of the drift layer where the P-doped region is absent, an anode metallization on the ohmic contact and on said cells, to form junction-barrier contacts and Schottky contacts respectively. The P-doped region has a grid-shaped layout separating from one another each cell and defining, together with the cells, an active area of the MPS diode. Each cell has a same geometry among quadrangular, quadrangular with rounded corners and circular; and the ohmic contact extends at the doped region with continuity along the grid-shaped layout.

Abstract: A stacked structure includes a lower structure and an upper structure. The lower structure includes at least one lower dielectric layer and at least one lower metal layer in contact with the lower dielectric layer. The upper structure includes at least one upper dielectric layer and at least one upper metal layer in contact with the upper dielectric layer. The upper dielectric layer includes a first upper dielectric layer attached to the lower structure. The first upper dielectric layer includes a first portion and a second portion. A difference between a thickness of the first portion and a thickness of the second portion is greater than a gap between a highest point of a top surface of the first upper dielectric layer and lowest point of the top surface of the first upper dielectric layer.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.

Abstract: An electronic device has a sealing part 90, a first terminal 11 projecting outward from a first side surface of the sealing part 90, a second terminal 13 projecting outward from a second side surface different from the first side surface of the sealing part 90, an electronic element 95 provided inside the sealing part 90, and a head part 40 coupled to the first terminal 11 and the second terminal and connected to a front surface of the semiconductor element 95 via a conductive adhesive 75.

Abstract: Methods of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high Ecrit semiconductors are presented. A dielectric layer is deposited on a high Ecrit substrate. The dielectric layer is etched to form a drift region. A refractory material is deposited on the substrate and dielectric layer. The refractory material is etched to form a gate length. Implant ionization is applied to form high-conductivity and high-critical field strength source with SAG and SAD features. The device is annealed to activate the contact regions. Alternately, a refractory material may be deposited on a high Ecrit substrate. The refractory material is etched to form a channel region. Implant ionization is applied to form high-conductivity and high Ecrit source and drain contact regions with SAG and SAD features. The refractory material is selectively removed to form the gate length and drift regions. The device is annealed to activate the contact regions.

Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.

Abstract: In a top-gate transistor in which an oxide semiconductor film, a gate insulating film, a gate electrode layer, and a silicon nitride film are stacked in this order and the oxide semiconductor film includes a channel formation region, nitrogen is added to regions of part of the oxide semiconductor film and the regions become low-resistance regions by forming a silicon nitride film over and in contact with the oxide semiconductor film. A source and drain electrode layers are in contact with the low-resistance regions. A region of the oxide semiconductor film, which does not contact the silicon nitride film (that is, a region overlapping with the gate insulating film and the gate electrode layer) becomes the channel formation region.