Patents Examined by Moin Rahman
  • Patent number: 10304741
    Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: May 28, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • Patent number: 10236212
    Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: March 19, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • Patent number: 10224468
    Abstract: A method of manufacturing a light emitting device includes: arranging first and second light emitting elements, each having a pair of electrodes disposed on a surface opposite to a main light emitting surface, on a base body adjacent to each other with the electrodes facing upward; forming a light shielding member at least covering the electrodes of each of the first and second light emitting elements and a portion between the first and second light emitting elements; forming recesses by removing portions of the light shielding member so that at least a portion of each of the electrodes of the first and second light emitting elements are exposed from the light shielding member; and forming electrically conductive members in the recesses so that each of the electrically conductive members is in contact with a corresponding one of the electrodes of the first and second light emitting elements.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 5, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Takahiro Tani, Hiroki Yuu, Toshiaki Moriwaki
  • Patent number: 10224319
    Abstract: An electrostatic protection element whose electrostatic breakdown resistance can be adjusted with a required minimum design change is provided. A semiconductor device includes an electrostatic protection element including a bipolar transistor whose base region and emitter region are electrically coupled together through a resistance region. At this time, the base region of the electrostatic protection element has a side including a facing portion that faces the collector region. The facing portion of the side includes an exposed portion that is exposed from an emitter wiring in plan view and a covered portion that is covered by the emitter wiring in plan view.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: March 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Eisuke Kodama
  • Patent number: 10211345
    Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10199405
    Abstract: A method of manufacturing a transistor display panel and a transistor display panel, the method including forming a polycrystalline silicon layer on a substrate; forming an active layer by patterning the polycrystalline silicon layer; forming a first insulating layer covering the substrate and the active layer; exposing the active layer by polishing the first insulating layer using a polishing apparatus; and forming a second insulating layer that contacts the first insulating layer and the active layer, wherein exposing the active layer by polishing the first insulating layer includes coating a first slurry on a surface of the first insulating layer, the first slurry reducing a polishing rate of the active layer.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joon-Hwa Bae, Byoung Kwon Choo, Byung Hoon Kang, Woo Jin Cho, Hyun Jin Cho, Jun Hyuk Cheon, Jee-Hyun Lee
  • Patent number: 10193038
    Abstract: Light emitting devices can be disposed on the front side of a transparent backplane. A laser beam can be irradiated through the transparent backplane and onto a component located on the front side of the transparent backplane. In one embodiment, the component may be a solder material portion that is reflowed to bond the light emitting devices to the transparent backplane. In another embodiment, the component may be a solder material bonded to a defective bonded light emitting device. In this case, the laser irradiation can reflow the solder material to dissociate the defective bonded light emitting device from the transparent backplane. In yet another embodiment, the component may be a device component that is electrically modified by the laser irradiation.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: January 29, 2019
    Assignee: GLO AB
    Inventors: Sharon N. Farrens, Anusha Pokhriyal
  • Patent number: 10186431
    Abstract: An integrated circuit (“IC”) package mold includes an upper mold platen that defines an upper mold cavity for receiving an upper substrate having a die attach side with a plurality of dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the upper substrate faces upwardly. A lower mold platen defines a lower mold cavity for receiving a lower substrate having a die attach side with a plurality dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the lower substrate faces downwardly.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: January 22, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Hiep Xuan Nguyen
  • Patent number: 10186649
    Abstract: A light emitting device includes a package, a light emitting element, and a sealing member. The package is equipped with a lead and a molded resin that holds the lead. The lead has an upper surface and a lower surface, and has a metal board and a plating layer. The plating layer includes a first plating layer that contains a nickel plating layer, a gold plating layer, and a silver plating layer, that is provided to an upper surface of the metal board, and that is not provided to a lower surface of the metal board. The light emitting element is mounted in the package. The sealing member seals the light emitting element.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: January 22, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Tomohide Miki
  • Patent number: 10186439
    Abstract: Semiconductor device fabrication systems and methods are provided. In an example, a semiconductor device fabrication system includes a semiconductor fabrication tool. Further, the semiconductor device fabrication system includes wireless sensors associated with the semiconductor fabrication tool. The wireless sensors measure process parameters of the fabrication tool and transmit wireless signals. The semiconductor device fabrication system also includes a sensor controller configured to identify the wireless sensors associated with the semiconductor fabrication tool and to receive the wireless signals from the wireless sensors. The semiconductor device fabrication system further includes a tool controller including a receiver for receiving data from the sensor controller. The tool controller is configured to sequentially assign system variable identifiers (SVID) to the data from the sensor controller, and to contextualize the data in data packets.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: January 22, 2019
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Boyd Finlay, Mark Reath, Eric Warren
  • Patent number: 10181529
    Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: January 15, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10177131
    Abstract: Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: January 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Lyong Kim, Jin-woo Park, Choongbin Yim, Younji Min
  • Patent number: 10170321
    Abstract: Described are methods of depositing a titanium aluminum nitride film on a substrate surface with a controlled amount of carbon. The methods include exposing a substrate surface to a titanium precursor, a nitrogen reactant and an aluminum precursor with purges of the unreacted titanium and aluminum precursors and unreacted nitrogen reactants between each exposure.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: January 1, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Wenyu Zhang, Wei V. Tang, Yixiong Yang, Chen-Han Lin, Yi Xu, Yu Lei, Naomi Yoshida, Lin Dong, Drew Phillips, Srividya Natarajan, Atashi Basu, Kaliappan Muthukumar, David Thompson, Paul F. Ma
  • Patent number: 10170467
    Abstract: A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding portion. The source line is disposed in the semiconductor substrate and partially extending below the protruding portion. The gate line is configured to surround and cover the protruding portion and electrically separated from the source line and the protruding portion. The memory cells are disposed on the semiconductor substrate and connected in series to the protruding portion at a top surface thereof.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: January 1, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Kuang-Hao Chiang, Dai-Ying Lee
  • Patent number: 10170477
    Abstract: A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region comprising a second channel region material; disposing a gate dielectric on the first channel region and second channel region; depositing a work function modifying material on the gate dielectric; disposing a mask over the work function modifying material deposited on the gate dielectric disposed on the first channel region; removing the work function modifying material from the unmasked gate dielectric disposed on the second channel region; removing the mask from the work function modifying material deposited on the gate dielectric disposed on the first channel region; forming a first gate electrode on the work function modifying material deposited on the first channel region and forming a second gate electrode on the gate dielectric disposed on the second channel region.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Gauri Karve, Derrick Liu, Robert R. Robison, Gen Tsutsui, Reinaldo A. Vega, Koji Watanabe
  • Patent number: 10170513
    Abstract: An image sensor arranged inside and on top of a semi-conductor substrate having a front surface and a rear surface, the sensor including a plurality of pixels, each including: a photosensitive area, a reading area, and a storage area extending between the photosensitive area and the reading area; a vertical insulated electrode including an opening of transfer between the photosensitive area and the storage area; and at least one insulation element among the following: a) a layer of an insulating material extending under the surface of the photosensitive area and of the storage area and having its front surface in contact with the rear surface of the electrode; and b) an insulating wall extending vertically in the opening, or under the opening.
    Type: Grant
    Filed: September 23, 2017
    Date of Patent: January 1, 2019
    Assignees: Commissariat à l'Energie Atomique et aux Energies, STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Yvon Cazaux, François Roy, Marie Guillon, Arnaud Laflaquiere
  • Patent number: 10158057
    Abstract: Packaged chip-on-board (COB) LED arrays are provided where a color conversion medium is distributed within a glass containment plate, rather than silicone, to reduce the operating temperature of the color conversion medium and avoid damage while increasing light output. A lighting device is provided comprising a chip-on-board (COB) light emitting diode (LED) light source, a light source encapsulant, a distributed color conversion medium, and a glass containment plate. The COB LED light source comprises a thermal heat sink framework and at least one LED and defines a light source encapsulant cavity in which the light source encapsulant is distributed over the LED. The glass containment plate is positioned over the light source encapsulant cavity and contains the distributed color conversion medium. The light source encapsulant is distributed over the LED at a thickness that is sufficient to encapsulate the LED and define encapsulant thermal conduction paths.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 18, 2018
    Assignee: CORNING INCORPORATED
    Inventors: Timothy James Orsley, William Richard Trutna, Nicholas Francis Borrelli, Lisa Ann Lamberson, Robert Michael Morena
  • Patent number: 10147783
    Abstract: Structures for an on-chip capacitor and methods of forming an on-chip capacitor. A metal terminal is formed that has a side edge. Metal fingers are formed that have a parallel arrangement. Floating islands comprised of a metal are formed and are electrically isolated from the metal fingers. Each of the metal fingers has an end and extends from the side edge of the metal terminal toward the end. Each of the floating islands is arranged in a spaced relationship with the end of a respective one of the metal fingers.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: December 4, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Atsushi Ogino, Vikrant Chauhan, Kong Boon Yeap, Ahmed Hassan
  • Patent number: 10134867
    Abstract: A method for manufacturing semiconductor device includes depositing a contact metal layer over a III-V compound layer. An anti-reflective coating (ARC) layer is deposited over the contact metal layer, and an etch stop layer is deposited over the ARC layer. The etch stop layer, the ARC layer, and the contact metal layer are etched to form a contact stack over the III-V compound layer. A conductive layer is deposited over the III-V compound layer, and the conductive layer is etched to form a gate field plate. The etch stop layer has an etch selectivity different from that of the conductive layer.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jheng-Sheng You, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
  • Patent number: 10128377
    Abstract: A method of making a semiconductor device includes forming a plurality of fins on a substrate, with the substrate including an oxide layer arranged beneath the plurality of fins. A sacrificial gate material is deposited on and around the plurality of fins. First trenches are formed in the sacrificial gate material. The first trenches extend through the oxide layer to a top surface of the substrate and are arranged between fins of the plurality of fin. First trenches are filled with a metal gate stack. Second trenches are formed in the sacrificial gate material, with a bottom surface of the second trenches being arranged over a bottom surface of the first trenches, and the second trenches being arranged between fins of the plurality of fins and alternating with the first trenches. The second trenches are filled with a metal gate stack.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terence B. Hook, Joshua M. Rubin, Tenko Yamashita