Patents Examined by Moin Rahman
  • Magnetic memory devices having perpendicular magnetic tunnel junction
    Patent number: 9831422
    Abstract: A magnetic memory device includes a first magnetic structure on a substrate, a second magnetic structure between the substrate and the first magnetic structure, and a tunnel barrier between the first and second magnetic structures. At least one of the first and second magnetic structures includes a perpendicular magnetic layer on the tunnel barrier, and a polarization enhancement layer interposed between the tunnel barrier and the perpendicular magnetic layer. Here, the polarization enhancement layer contains cobalt, iron, and at least one of the elements of Group IV, and the polarization enhancement layer has a magnetization direction perpendicular to or substantially perpendicular to a top surface of the substrate.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: November 28, 2017
    Assignees: SAMSUNG ELECTRONICS CO., LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Woojin Kim, Joonmyoung Lee, Yong Sung Park, Stuart S. P. Parkin
  • Light-emitting diode
    Patent number: 9825087
    Abstract: A light-emitting diode is provided. The light-emitting diode comprises: a first light-emitting structure, comprising: a first area; a second area; a first isolation path having an electrode isolation layer between the first area and the second area; an electrode contact layer covering the first area; and an electrical connecting structure covering the second area; wherein each of the first area and the second area sequentially comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, and the electrode contact layer covers a sidewall of the first area.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: November 21, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Tsung-Hsien Yang, Han-Min Wu, Jhih-Sian Wang, Yi-Ming Chen, Tzu-Ghieh Hsu
  • Semiconductor manufacturing apparatus and method of operating the same
    Patent number: 9799546
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes an electrostatic chuck that includes a base and a first electrode provided on the base and is configured to electrostatically adsorb a wafer on the first electrode. The apparatus further includes a measurement module configured to measure potential of the wafer. The apparatus further includes a controller configured to adjust potential of the base based on the potential of the wafer and to adjust potential of the first electrode based on the potential of the wafer or the base, when the potential of the wafer measured by the measurement module changes.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: October 24, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yuya Matsuda
  • Advanced copper interconnects with hybrid microstructure
    Patent number: 9799605
    Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Wafer structure for electronic integrated circuit manufacturing
    Patent number: 9799516
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: October 24, 2017
    Assignee: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph M. Benedetto
  • Wafer structure for electronic integrated circuit manufacturing
    Patent number: 9799653
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: October 24, 2017
    Assignee: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph M. Benedetto
  • Wafer structure for electronic integrated circuit manufacturing
    Patent number: 9786608
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: October 10, 2017
    Assignee: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph M. Benedetto
  • Strained semiconductor device
    Patent number: 9773870
    Abstract: A semiconductor device comprises a first semiconductor fin having a first width, the first semiconductor fin is arranged on a first portion of the strain relaxation buffer layer, where the first portion of the strain relaxation buffer layer has a second width and a second semiconductor fin having a width substantially similar to the first width, the second semiconductor fin is arranged on a second portion of the strain relaxation buffer layer, where the second portion of the strain relaxation buffer layer has a third width. A gate stack is arranged over a channel region of the first fin and a channel region of the second fin.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: September 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu
  • Method for producing strained semi-conductor blocks on the insulating layer of a semi-conductor on insulator substrate
    Patent number: 9761607
    Abstract: A method for producing a microelectronic device is provided, including forming on an insulating layer of a semi-conductor on insulator type substrate, a first semi-conductor block covered with a first strain zone configured to induce a compressive strain in the first block and a second semi-conductor block covered with a second strain zone configured to induce a tensile strain in the second block, the first block and the second block each being formed of a lower region based on amorphous semi-conductor material, covered with an upper region of crystalline semi-conductor material in contact with one of the strain zones; and recrystallizing the lower region of the first and second blocks while using the upper region of crystalline material as starting zone for a recrystallization front.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 12, 2017
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Shay Reboh, Perrine Batude, Sylvain Maitrejean, Frederic Mazen
  • Three-dimensional stacking structure and manufacturing method thereof
    Patent number: 9748206
    Abstract: A three-dimensional stacking structure and the manufacturing method(s) thereof are described. The stacking structure includes at least a bottom die, a top die and a spacer protective structure. The bottom die include contact pads in the non-bonding region. The top die is stacked on the bottom die without covering the contact pads of the bottom die and the bottom die is bonded with the top die through bonding structures there-between. The spacer protective structure is disposed on the bottom die and covers the top die to protect the top die. By forming an anti-bonding layer before stacking the top dies to the bottom dies, the top die can be partially removed to expose the contact pads of the bottom die for further connection.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Peter Yu Fei Huang, Chaochieh Tsai
  • Package-on-package (PoP) device comprising bi-directional thermal electric cooler
    Patent number: 9746889
    Abstract: A package-on-package (PoP) device includes a first package, a second package, and a bi-directional thermal electric cooler (TEC). The first package includes a first substrate and a first die coupled to the first substrate. The second package is coupled to the first package. The second package includes a second substrate and a second die coupled to the second substrate. The TEC is located between the first die and the second substrate. The TEC is adapted to dynamically dissipate heat back and forth between the first package and the second package. The TEC is adapted to dissipate heat from the first die to the second die in a first time period. The TEC is further adapted to dissipate heat from the second die to the first die in a second time period. The TEC is adapted to dissipate heat from the first die to the second die through the second substrate.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: August 29, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Rajat Mittal, Hee Jun Park, Peng Wang, Mehdi Saeidi, Arpit Mittal
  • Semiconductor chip, method for producing a semiconductor chip and method for soldering a semiconductor chip to a carrier
    Patent number: 9741639
    Abstract: A semiconductor chip includes a semiconductor body and a chip metallization applied on the semiconductor body. The chip metallization has an underside facing away from the semiconductor body. The chip further includes a layer stack applied to the underside of the chip metallization and having a number N1?1 or N1?2 of first partial layers and a number N2?2 of second partial layers. The first partial layers and the second partial layers are arranged alternately and successively such that at least one of the second partial layers is arranged between the first partial layers of each first pair of the first partial layers and such that at least one of the first partial layers is arranged between the second partial layers of each second pair of the second partial layers.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 22, 2017
    Assignee: Infineon Technologies AG
    Inventors: Frank Umbach, Niels Oeschler, Kirill Trunov
  • Method for forming semiconductor device structure with fine line pitch and fine end-to-end space
    Patent number: 9735028
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hao Chen, Yu-Shu Chen, Yu-Cheng Liu
  • Device structure and manufacturing method using HDP deposited source-body implant block
    Patent number: 9716156
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Grant
    Filed: May 2, 2015
    Date of Patent: July 25, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K Lui
  • Lighting device with plural fluorescent materials
    Patent number: 9711686
    Abstract: Provided is a light-emitting device that has a high emission efficiency, excellent stability and temperature properties, and that generates light having a high color rendering property sufficient for practical use. This semiconductor light-emitting device comprises a semiconductor light-emitting element that emits blue light, a green phosphor that absorbs the blue light and emits green light, and an orange phosphor that absorbs the blue light and emits orange light, and is characterized in that the orange phosphor is an Eu-activated ?-SiAlON phosphor having an emission spectrum peak wavelength within a range of 595 to 620 nm.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: July 18, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kenichi Yoshimura, Kohsei Takahashi, Hiroshi Fukunaga
  • EL display device
    Patent number: 9704925
    Abstract: An EL display device including a light emitter configured to emit at least red, green, and blue light; and a thin film transistor array that controls light emission. The light emitter includes light-emitting layers within areas defined by a bank that emit at least red, green, and blue light. The light emitter further includes electrodes that extend under the bank and hole transport layers that are above the electrodes within the areas defined by the bank, the light-emitting layers being formed on the hole transport layers. The hole transport layers each have a main portion and a peripheral protrusion in contact with a side surface of the bank that protrudes upwards from the main portion. The light-emitting layers each have a peripheral protrusion in contact with a side surface of the bank, formed above a corresponding one of the peripheral protrusions.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: July 11, 2017
    Assignee: JOLED INC.
    Inventors: Toshiyuki Akiyama, Hiroyuki Ajiki
  • Flip-chip mounted semiconductor device
    Patent number: 9704771
    Abstract: Provided is a flip-chip mounted semiconductor device in which a crack is less likely to develop. Flip chip mounting is carried out under the condition that no oxide film exists on the scribe region so as to eliminate the interface between the oxide film that remains on the scribe region and the silicon substrate from which a crack may develop. As a result, the circuit board, the encapsulant, and the silicon substrate are stacked at an end portion of the semiconductor chip.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 11, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Yoichi Mimuro, Kotaro Watanabe, Yukimasa Minami
  • Substrate comprising stacks of interconnects, interconnect on solder resist layer and interconnect on side portion of substrate
    Patent number: 9691694
    Abstract: An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: June 27, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Uei-Ming Jow, Young Kyu Song, Jong-Hoon Lee, Xiaonan Zhang, Mario Francisco Velez
  • Semiconductor device having buried channel array
    Patent number: 9685519
    Abstract: A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: June 20, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Na-Ra Kim, Seung-Hwan Kim, Sung-Hee Lee, Dae-Sin Kim, Ji-Young Kim, Dong-Soo Woo
  • Light emitting apparatus, illumination apparatus and display apparatus
    Patent number: 9679536
    Abstract: A light emitting apparatus including: one or a plurality of light emitting devices each having a plurality of electrodes and each emitting light from the upper surface of the light emitting device; a plurality of terminal electrodes provided on the lower side of the light emitting devices in a positional relation with the light emitting devices and electrically connected to the electrodes of the light emitting devices; a first metal line brought into contact with the upper surfaces of the light emitting devices and one of the terminal electrodes, provided at a location separated away from side surfaces of the light emitting devices and created in a film creation process; and an insulator in which the light emitting devices and the first metal line are embedded.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: June 13, 2017
    Assignee: SONY CORPORATION
    Inventors: Naoki Hirao, Katsuhiro Tomoda