Patents Examined by Moin Rahman
  • Patent number: 10038049
    Abstract: A display device, includes a substrate; first to fourth subpixels sequentially arranged on the substrate; a first power line on a left side of the first subpixel and shared by the first and second subpixels; a sensing line between the second subpixel and the third subpixel and shared by the first to fourth subpixels; a second power line on a right side of the fourth subpixel and shared by the third and fourth subpixels; and a first data line on the left side of the first subpixel, a second data line on a right side of the second subpixel, a third data line on a left side of the third subpixel, and a fourth data line on the right side of the fourth subpixel. The first and second power lines and the sensing line are disposed on a layer different from the first to fourth data lines.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 31, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Byeonguk Gang, Jongsik Shim, Hyunjin Kim, Joondong Kim
  • Patent number: 10020192
    Abstract: A method for forming polysilicon on a semiconductor substrate that include providing amorphous silicon on a semiconductor substrate, exposing at least an area of the amorphous silicon to a first laser beam and a second laser beam, characterized in that during exposing the area to the second laser beam no displacement of the laser beam relative to the area occurs. In addition, the use of such method for producing large grain polysilicon. In particular, the use of such method for producing vertical grain polysilicon. Further, the use of such method for producing sensors, MEMS, NEMS, Non Volatile Memory, Volatile memory, NAND Flash, DRAM, Poly Si contacts and interconnects.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: July 10, 2018
    Assignee: LASER SYSTEMS & SOLUTIONS OF EUROPE
    Inventor: Fulvio Mazzamuto
  • Patent number: 10014379
    Abstract: One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: July 3, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Xiuyu Cai
  • Patent number: 10014380
    Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 3, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
  • Patent number: 10014278
    Abstract: A semiconductor chip includes a substrate, through-electrodes passing through the substrate, and a dielectric layer formed between the substrate and the through-electrodes and having a dielectric constant decreasing structure.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: July 3, 2018
    Assignee: SK hynix Inc.
    Inventor: Ho Young Son
  • Patent number: 10014179
    Abstract: Methods for processing a substrate include: (a) depositing a cobalt layer to a first thickness within a first plurality of features and a second plurality of features formed in a substrate, wherein each of the first plurality of features and each of the second plurality of features comprises an opening, and wherein a width of the openings of the first plurality of features is less than a width of the openings of the second plurality of features; and (b) heating the substrate to a first temperature to fill the first plurality of features with cobalt material while simultaneously depositing a fill material on the substrate to fill the second plurality of features.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: July 3, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Rong Tao, Tae Hong Ha, Xianmin Tang, Joung Joo Lee
  • Patent number: 10002925
    Abstract: A semiconductor device comprises a first semiconductor fin having a first width, the first semiconductor fin is arranged on a first portion of the strain relaxation buffer layer, where the first portion of the strain relaxation buffer layer has a second width and a second semiconductor fin having a width substantially similar to the first width, the second semiconductor fin is arranged on a second portion of the strain relaxation buffer layer, where the second portion of the strain relaxation buffer layer has a third width. A gate stack is arranged over a channel region of the first fin and a channel region of the second fin.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: June 19, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10002892
    Abstract: The present invention relates to a solid-state imaging device. In a pixel array section in the solid-state imaging device, a vertical signal line is provided right under power supply wiring apart from a floating diffusion region in order to reduce load capacitance of the vertical signal line. Furthermore, the power supply wiring is wired to make a cover rate of each vertical signal line with respect to the power supply wiring nearly uniform. As a result, it is possible to suppress variation of load capacitance of the vertical signal line for each pixel. It becomes possible to suppress deviation in a black level, variation of charge transfer, and variation of settling. It becomes possible to obtain an image with higher quality.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: June 19, 2018
    Assignee: Sony Corporation
    Inventors: Yusuke Uesaka, Atsuhiko Yamamoto
  • Patent number: 10002756
    Abstract: A method for fabricating a Fin-FET device includes forming a plurality of discrete fin structures on a substrate with a bottom portion of the sidewall surfaces covered in an isolation layer, and forming a dielectric layer on the isolation layer and the fin structures with an opening formed across the fin structures and exposing a portion of the isolation layer and the fin structures. The method further includes forming a first oxidation layer on the exposed surfaces of the fin structures, and then forming a second oxidation layer between the first oxidation layer and the surfaces of the fin structures through a first annealing process. The method then includes forming a gate dielectric layer on the first oxidation layer, forming a sacrificial adsorption layer on the gate dielectric layer, performing a second annealing process, and then forming a gate electrode layer to fill the opening formed in the dielectric layer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 19, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 9971437
    Abstract: The present application discloses an array substrate comprising an active layer; and a plurality of touch electrodes in a same layer as the active layer.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: May 15, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenlin Zhang, Woo-Bong Lee
  • Patent number: 9954085
    Abstract: A tunnel field-effect transistor device includes a p-type GaN source layer, an ntype GaN drain layer, and an interlayer interfaced between the source-layer and the drain layer. These devices employ polarization engineering in GaN/InN heterojunctions to achieve appreciable interband tunneling current densities. In one example, the interlayer includes an Indium Nitride (InN) layer. In one example, the interlayer includes a graded Indium gallium nitride layer and an InN layer. In one example, the interlayer may include a graded Indium gallium nitride (InxGa1-xN) layer and an Indium gallium nitride (InGaN) layer. In one example, the tunnel field-effect transistor device includes an in-line configuration. In one example, the tunnel field-effect transistor device includes a side-wall configuration. In one example, the tunnel field-effect transistor device includes a nanowire cylindrical gate-all-around geometry to achieve a high degree of gate electrostatic control.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: April 24, 2018
    Assignee: University of Notre Dame due Lac
    Inventors: Patrick Fay, Lina Cao, Debdeep Jena, Wenjun Li
  • Patent number: 9947792
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, in which the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: April 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Chih-Kai Hsu, Yu-Hsiang Hung, Jyh-Shyang Jenq
  • Patent number: 9947552
    Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes disposing a mold over the carrier substrate. The method further includes forming a protection layer between the mold and the carrier substrate to surround the semiconductor die and the conductive structures. In addition, the method includes removing the mold.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Chao Chen, Chih-Wei Lin, Meng-Tse Chen, Hui-Min Huang, Ming-Da Cheng, Kuo-Lung Pan, Wei-Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai
  • Patent number: 9947724
    Abstract: A method of fabricating a CMOS logic device with SWCNTs includes forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor. Each of the NMOS and PMOS transistors has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each PMOS transistor and the gate of each NMOS transistor are configured to alternatively receive at least one input voltage. At least one of the drain of the PMOS transistor and the drain of the NMOS transistor is configured to output an output voltage.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: April 17, 2018
    Assignees: NORTHWESTERN UNIVERSITY, REGENTS OF THE UNIVERSITY OF MINNESOTA
    Inventors: Mark C. Hersam, Michael L. Geier, Pradyumna L. Prabhumirashi, Weichao Xu, Hyungil Kim
  • Patent number: 9947543
    Abstract: The present disclosure relates to a semiconductor memory, device and a method of forming a semiconductor memory device. The method of manufacturing a semiconductor memory device, includes forming a tunnel insulation layer and a floating gate on a semiconductor substrate of an active region, forming a trench in the semiconductor substrate of an isolation region, forming, in the trench, a sacrificial layer having an upper surface positioned higher than a surface of the semiconductor substrate, forming a capping layer over the sacrificial layer, and forming an air gap by removing the sacrificial layer without removing the capping layer.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: April 17, 2018
    Assignee: SK Hynix Inc.
    Inventors: Tae Kyung Kim, Jung Myoung Shim, Myung Kyu Ahn, Sung Soon Kim, Woo Duck Jung
  • Patent number: 9941219
    Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Digvijay A. Rorane, Ian En Yoon Chin, Daniel N. Sobieski
  • Patent number: 9941384
    Abstract: A semiconductor device includes a first III-V compound layer on a substrate, a second III-V compound layer on the first III-V compound layer, in which a material of the first III-V compound layer is different from that of the second III-V compound layer, a gate metal stack disposed on the second III-V compound layer, a source contact and a drain contact disposed at opposite sides of the gate metal stack, a gate field plate disposed between the gate metal stack and the drain contact, an anti-reflective coating (ARC) layer formed on the source contact and the drain contact, and an etch stop layer formed on the ARC layer.
    Type: Grant
    Filed: August 29, 2015
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jheng-Sheng You, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
  • Patent number: 9922867
    Abstract: A method for transferring a useful layer onto a carrier substrate comprises formation of an embrittlement plane by implantation of light species into a first substrate in such a manner as to define the bounds of a useful layer between the plane and a surface of the first substrate, mounting of the carrier substrate onto a surface of the first substrate so as to form an assembly to be fractured, and thermal fracture treatment of the first substrate along the embrittlement plane in such a manner as to transfer the useful layer onto a support. During the thermal fracture treatment, the degree of peripheral adhesion is reduced at an interface between the carrier substrate and the first substrate.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: March 20, 2018
    Assignee: Soitec
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Patent number: 9922833
    Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: March 20, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mark Ramsbey, Chun Chen, Sameer Haddad, Kuo Tung Chang, Unsoon Kim, Shenqing Fang, Yu Sun, Calvin Gabriel
  • Patent number: 9919915
    Abstract: Methods and systems for MEMS devices with dual damascene formed electrodes is disclosed and may include forming first and second dielectric layers on a semiconductor substrate that includes a conductive layer at least partially covered by the first dielectric layer; removing a portion of the second dielectric layer; forming vias through the second dielectric layer and at least a portion of the second dielectric layer, where the via extends to the conductive layer; forming electrodes by filling the vias and a volume that is the removed portion of the second dielectric layer with a first metal; and coupling a micro-electro-mechanical systems (MEMS) substrate to the semiconductor substrate. A third dielectric layer may be formed between the first and second dielectric layers. A metal pad may be formed on at least one electrode by depositing a second metal on the electrode and removing portions of the second metal, which may be aluminum.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: March 20, 2018
    Assignee: INVENSENSE, INC.
    Inventors: Chunchieh Huang, Peter Smeys