Patents Examined by Moin Rahman
  • Patent number: 10128214
    Abstract: The present invention discloses a substrate where the lateral surface of the substrate is formed to expose at least one portion of a via(s) for circuit connection. The substrate comprises a plurality of insulating layers; and a plurality of conductive layers separated by the plurality of insulating layers. A first lateral surface of the substrate is formed by the plurality of conductive layers and the plurality of insulating layers. The first lateral surface of the substrate comprises at least one first portion of a first via filled with a first conductive material.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: November 13, 2018
    Assignee: CYNTEC CO., LTD.
    Inventors: Bau-Ru Lu, Ming-Chia Wu, Shao Wei Lu
  • Patent number: 10121659
    Abstract: The present invention, when forming a pattern on a substrate, forms a film of a block copolymer containing at least two polymers on the substrate, heats the film of the block copolymer under a solvent vapor atmosphere to subject the block copolymer to phase separation, and removes one of the polymers in the film of the phase-separated block copolymer, thereby accelerating fluidization of the polymers of the block copolymer to enable acceleration of the phase separation.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: November 6, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Makoto Muramatsu, Takahiro Kitano, Tadatoshi Tomita, Keiji Tanouchi
  • Patent number: 10115630
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shiou Chen, Chih-Yuan Ting
  • Patent number: 10103130
    Abstract: An LED module includes a substrate, one or more LED chips supported by a main surface of the substrate, and wirings. The substrate has one or more through holes penetrating from the main surface to a rear surface. The wirings are formed on the substrate and make electrical conduction with the LED chips. The wirings include pads which are formed on the main surface and make electrical conduction with the LED chips, rear surface electrodes which are formed on the rear surface, and through wirings which make electrical conduction between the pads and the rear surface electrodes and are formed on the inner sides of the through holes.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 16, 2018
    Assignee: Rohm Co., Ltd.
    Inventors: Masahiko Kobayakawa, Takashi Moriguchi
  • Patent number: 10103231
    Abstract: According to one embodiment, a semiconductor device includes a first element portion. The first element portion includes first and second semiconductor layers, first, second and third electrodes, and a first insulating layer. The first semiconductor layer includes Alx1Ga1-x1N (0?x1<1). The first electrode is separated from the first semiconductor layer. The first electrode includes a polycrystal of a nitride of one of Al or B. The second semiconductor layer includes Alx2Ga1-x2N (x1<x2<1). The second semiconductor layer includes first to third regions. The first region is positioned between the second and third regions. The first region is provided between the first semiconductor layer and the first electrode. The first insulating layer is provided between the first region and the first electrode. The second electrode is electrically connected to the second region. The third electrode is electrically connected to the third region.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: October 16, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Koyama, Hisashi Saito, Tatsuo Shimizu, Shinya Nunoue
  • Patent number: 10090202
    Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: October 2, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • Patent number: 10090306
    Abstract: A method for fabricating a Fin-FET includes forming a plurality of fin structures, an isolation layer, and an interlayer dielectric layer on an NMOS region of a substrate, forming a first opening in the interlayer dielectric layer to expose a portion of the fin structures. A region adjacent to a joint between a bottom surface and a sidewall surface of the first opening is a corner region. The method includes forming a high-k dielectric layer on the bottom and the sidewall surfaces of the first opening, a barrier layer on the high-k dielectric layer, and an N-type work function layer containing aluminum ions on the barrier layer. The method further includes performing a back-flow annealing process such that the portion of N-type work function layer at the corner region is thickened and contains diffused aluminum ions. Finally, the method includes forming a metal layer on the N-type work function layer.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: October 2, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10090167
    Abstract: Semiconductor devices and methods of forming the same are disclosed. A dielectric layer is formed over an underlying layer. A first mask layer and a second mask layer are formed on the dielectric layer such that the first mask layer is interposed between the second mask layer and the dielectric layer. An opening is formed in the first mask layer, the second mask layer and the dielectric layer. Subsequently, the second mask layer is removed. The opening is extended and corners of the first mask layer are rounded. A conductive feature is formed in the extended opening.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chien-Chih Chiu, Ming-Chung Liang
  • Patent number: 10084156
    Abstract: A light-emitting element with which a reduction in power consumption and an improvement in productivity of a display device can be achieved is provided. A technique of manufacturing a display device with high productivity is provided. The light-emitting element includes an electrode having a reflective property, and a first light-emitting layer, a charge generation layer, a second light-emitting layer, and an electrode having a light-transmitting property stacked in this order over the electrode having a reflective property. The optical path length between the electrode having a reflective property and the first light-emitting layer is one-quarter of the peak wavelength of the emission spectrum of the first light-emitting layer. The optical path length between the electrode having a reflective property and the second light-emitting layer is three-quarters of the peak wavelength of the emission spectrum of the second light-emitting layer.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: September 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Toshiki Sasaki, Nobuharu Ohsawa, Takahiro Ushikubo, Shunpei Yamazaki
  • Patent number: 10079159
    Abstract: Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. The openings are formed by removing materials, such as by laser drill, surrounding the end-portions of the TPVs. The openings surrounding the end-portions of the TPVs of the die package enable solders of the bonding structures formed between another die package to remain in the openings without sliding and consequently increases yield and reliability of the bonding structures. Polymers may also be added to fill the openings surrounding the TPVs or even the space between the die packages to reduce cracking of the bonding structures under stress.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Li-Hui Cheng
  • Patent number: 10079225
    Abstract: Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. The openings are formed by removing materials, such as by laser drill, surrounding the end-portions of the TPVs. The openings surrounding the end-portions of the TPVs of the die package enable solders of the bonding structures formed between another die package to remain in the openings without sliding and consequently increases yield and reliability of the bonding structures. Polymers may also be added to fill the openings surrounding the TPVs or even the space between the die packages to reduce cracking of the bonding structures under stress.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Li-Hui Cheng
  • Patent number: 10074623
    Abstract: A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a dielectric layer, an alignment, and a redistribution conductive layer. The dielectric layer covers the conductor and includes at least one contact opening for exposing the conductor. The alignment mark is disposed on the dielectric layer. The alignment mark includes a base portion on the dielectric layer and a protruding portion on the base portion, wherein a ratio of a maximum thickness of the protruding portion to a thickness of the base portion is smaller than 25%. The redistribution conductive layer is disposed on the dielectric layer. The redistribution conductive layer includes a conductive via, and the conductive via is electrically connected to the conductor through the contact opening. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzung-Hui Lee, Hung-Jui Kuo, Ming-Che Ho, Tzu-Yun Huang
  • Patent number: 10049926
    Abstract: A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern can be formed above the dielectric material stack. A second pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure. The first pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure while the second pattern is transferred through the via level dielectric material layer to form integrated line and via trenches, which are filled with a conductive material to form integrated line and via structures.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Junjing Bao, Wai-Kin Li
  • Patent number: 10050186
    Abstract: A light emitting device includes a molded package and one or more light emitting components. The molded package includes a recess, two leads, and a molded resin part. A part of the recess is defined by a side wall formed from the molded resin part. At least one of the two leads includes an upper-surface portion exposed from a bottom surface of the recess. The at least one of the two leads includes a groove at an upper surface thereof. The groove is filled with a part of the molded resin part. The part of the molded resin part includes a first portion and a second portion. The first portion is exposed from the bottom surface of the recess. The second portion connects with a bottom surface of the side wall.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: August 14, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Shimpei Sasaoka, Takuya Nakabayashi
  • Patent number: 10043919
    Abstract: Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: August 7, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
  • Patent number: 10043700
    Abstract: A method of fabricating a semiconductor-on-diamond composite substrate, the method comprising: (i) starting with a native semiconductor wafer comprising a native silicon carbide substrate on which a compound semiconductor is disposed; (ii) bonding a silicon carbide carrier substrate to the compound semiconductor; (iii) removing the native silicon carbide substrate; (iv) forming a nucleation layer over the compound semiconductor; (v) growing polycrystalline chemical vapor deposited (CVD) diamond on the nucleation layer to form a composite diamond-compound semiconductor-silicon carbide wafer, and (vi) removing the silicon carbide carrier substrate y laser lift-off to achieve a layered structure comprising the compound semiconductor bonded to the polycrystalline CVD diamond via the nucleation layer, wherein in step (ii) the silicon carbide carrier substrate is bonded to the compound semiconductor via a laser absorption material which absorbs laser light, wherein the laser has a coherence length shorter than a th
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: August 7, 2018
    Assignee: RFHIC CORPORATION
    Inventor: Daniel Francis
  • Patent number: 10043764
    Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: August 7, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Huang Liu, Sarasvathi Thangaraju, Chun Yu Wong
  • Patent number: 10043706
    Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: August 7, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Yuan Ting, Ya-Lien Lee, Chung-Wen Wu, Jeng-Shiou Chen
  • Patent number: 10043848
    Abstract: In order to form a light receiving element having high reliability and a MOS transistor together on the same silicon substrate, after forming a gate electrode of the MOS transistor, a gate oxide film in a light receiving element forming region is removed. Then, a thermal oxide film is newly formed in the light receiving element forming region, and ion implantation is performed in the light receiving element forming region through the thermal oxide film such that a shallow pn junction is formed.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 7, 2018
    Assignee: SII Semiconductor Corporation
    Inventor: Toshiro Futatsugi
  • Patent number: 10038030
    Abstract: A light-emitting diode comprises: a first light-emitting structure, comprising: a first area comprising a side wall; a second area; and a first isolation path having an electrode isolation layer between the first area and the second area, wherein the side wall of the first area is in the first isolation path; an electrode contact layer covering the side wall of the first area, wherein the electrode contact layer is separated from electrode isolation layer; an electrical connecting structure covering the second area; and an electrical contact layer under the electrical connecting structure, wherein the electrical contact layer directly contacts the electrical connecting structure; wherein each of the first area and the second area sequentially comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: July 31, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Tsung-Hsien Yang, Han-Min Wu, Jhih-Sian Wang, Yi-Ming Chen, Tzu-Ghieh Hsu