Patents Examined by Moin Rahman
  • Patent number: 9917191
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: March 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Manfred Eller, Jin-Ping Han
  • Patent number: 9917063
    Abstract: A semiconductor die package includes a semiconductor die, a film for improving die warpage bonded to a first face of the semiconductor die, a plurality of electrically conductive bumps formed on a second face of the semiconductor die, a substrate onto which the electrically conductive bumps of the second face of the semiconductor die are bonded to electrically connect the semiconductor die and the substrate, and a mold compound applied these components to form an exposed surface of the semiconductor die package that is coplanar with an exposed surface of the film.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: March 13, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Jin Seong Kim, Byong Woo Cho, Cha Gyu Song
  • Patent number: 9917022
    Abstract: A silicon single crystal wafer is provided. The silicon single crystal wafer includes an IDP which is divided into an NiG region and an NIDP region, wherein the IDP region is a region where a Cu based defect is not detected, the NiG region is a region where an Ni based defect is detected and the NIPD region is a region where an Ni based defect is not detected.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 13, 2018
    Assignee: SK SILTRON CO., LTD.
    Inventor: Woo Young Sim
  • Patent number: 9917234
    Abstract: A method of manufacturing a light emitting device includes: arranging a first light emitting element and a second light emitting element, each having a pair of first and second electrodes disposed on a surface opposite to a main light emitting surface, on a base body adjacent to each other with the pair of electrodes facing upward; forming a pair of electrically conductive members each extending between one of the pair of electrodes of the first light emitting element and a corresponding one of the pair of electrodes of the second light emitting element; forming a light shielding member at least covering between the first and second light emitting elements; and cutting the pair of electrically conductive members and the light shielding member between the first and second light emitting elements, along a direction substantially perpendicular to the main light emitting surface of each of the first and second light emitting elements.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: March 13, 2018
    Assignee: Nichia Corporation
    Inventors: Takahiro Tani, Hiroki Yuu, Toshiaki Moriwaki
  • Patent number: 9917166
    Abstract: A semiconductor device includes a substrate comprising a source region and a drain region, a bit storing element formed on the substrate, a memory gate structure, a first insulating layer formed on the substrate, a second insulating layer formed on the substrate, and a select gate structure formed on the first insulating layer. The second insulating layer is formed on the memory gate structure and the select gate structure and between the memory gate structure and the select gate structure.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: March 13, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
  • Patent number: 9917124
    Abstract: An image sensor arranged inside and on top of a semi-conductor substrate having a front surface and a rear surface, the sensor including a plurality of pixels, each including: a photosensitive area, a reading area, and a storage area extending between the photosensitive area and the reading area; a vertical insulated electrode including an opening of transfer between the photosensitive area and the storage area; and at least one insulation element among the following: a) a layer of an insulating material extending under the surface of the photosensitive area and of the storage area and having its front surface in contact with the rear surface of the electrode; and b) an insulating wall extending vertically in the opening, or under the opening.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: March 13, 2018
    Assignee: Commissariat à l'Energie Atomique et aux Energies Alternatives
    Inventors: Yvon Cazaux, François Roy, Arnaud Laflaquiere, Marie Guillon
  • Patent number: 9911715
    Abstract: The present invention discloses a three-dimensional package structure which can achieve a relatively high utilization of an internal space thereof, so that the size of electronic package structure can be reduced. The three-dimensional package structure comprises a substrate, a first plurality of discrete conductive components and a connecting structure. The substrate has a top surface and a bottom surface. The first plurality of discrete conductive components are disposed over the bottom surface of the substrate. The connecting structure is disposed over the bottom surface of the substrate for encapsulating the first plurality of discrete electronic components. The connecting structure comprises at least one insulating layer and a plurality of conductive patterns separated by the at least one insulating layer. The plurality of conductive patterns are disposed over the first plurality of discrete electronic components for electrically connecting the first plurality of discrete electronic components.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: March 6, 2018
    Assignee: CYNTEC CO., LTD.
    Inventors: Bau-Ru Lu, Ming-Chia Wu, Shao Wei Lu
  • Patent number: 9905647
    Abstract: A tunnel field-effect transistor device includes a p-type GaN source layer, an n-type GaN drain layer, and an interlayer interfaced between the source-layer and the drain layer. In one example, the interlayer includes an Indium Nitride (InN) layer. In one example, the interlayer includes a graded Indium gallium nitride layer and an InN layer. In one example, the interlayer may include a graded Indium gallium nitride (InxGa1-xN) layer and an Indium gallium nitride (InGaN) layer. In one example, the tunnel field-effect transistor device includes an in-line configuration. In one example, the tunnel field-effect transistor device includes a side-wall configuration.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: February 27, 2018
    Assignee: University of Notre Dame du Lac
    Inventors: Patrick Fay, Wenjun Li, Debdeep Jena
  • Patent number: 9899342
    Abstract: A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a dielectric layer, an alignment, and a redistribution conductive layer. The dielectric layer covers the conductor and includes at least one contact opening for exposing the conductor. The alignment mark is disposed on the dielectric layer. The alignment mark includes a base portion on the dielectric layer and a protruding portion on the base portion, wherein a ratio of a maximum thickness of the protruding portion to a thickness of the base portion is smaller than 25%. The redistribution conductive layer is disposed on the dielectric layer. The redistribution conductive layer includes a conductive via, and the conductive via is electrically connected to the conductor through the contact opening. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzung-Hui Lee, Hung-Jui Kuo, Ming-Che Ho, Tzu-Yun Huang
  • Patent number: 9893027
    Abstract: A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 13, 2018
    Assignee: NXP USA, INC.
    Inventors: David F. Abdo, Sivanesan A/L Sathiapalan
  • Patent number: 9893255
    Abstract: A molded package includes a recess, leads, and a molded resin part. The leads include a first lead and a second lead. A part of the recess is defined by a side wall formed from the molded resin part. At least one of the leads includes an upper-surface portion exposed from a bottom surface of the recess. The at least one of the leads includes a groove formed on an upper surface thereof partially below the side wall. The first lead includes an additional groove provided on an upper surface thereof along a side of the first lead positioned opposite a side of the second lead.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: February 13, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Shimpei Sasaoka, Takuya Nakabayashi
  • Patent number: 9887330
    Abstract: A light-emitting apparatus includes a reflective layer including a cavity that penetrates the reflective layer from a top surface to a bottom surface of the reflective layer; a light-emitting device disposed in the cavity, the light-emitting device including a light-emitting stack and an electrode connected to the light-emitting stack at a bottom surface of the light-emitting stack; and a wavelength conversion layer that fills the cavity and covers a top surface and a side surface of the light-emitting device, wherein the wavelength conversion layer exposes at least a portion of the electrode to an outside.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: February 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hun-yong Park, Sang-hyun Lee, Gam-han Yong, Eui-seok Kim
  • Patent number: 9887102
    Abstract: A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically connected to the substrate; an encapsulant formed on the substrate and encapsulating semiconductor elements, wherein the encapsulant has a plurality of round holes formed between the semiconductor elements; and an electromagnetic shielding structure formed in each of the round holes and connected to the grounding structure to achieve electromagnetic shielding effects. A method for forming the multi-chip package is also provided.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: February 6, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Tai-Tsung Hsu, Cheng-Yu Chiang, Miao-Wen Chen, Wen-Jung Chiang, Hsin-Hung Lee
  • Patent number: 9884827
    Abstract: A method of forming a structure having selectively placed carbon nanotubes, a method of making charged carbon nanotubes, a bi-functional precursor, and a structure having a high density carbon nanotube layer with minimal bundling. Carbon nanotubes are selectively placed on a substrate having two regions. The first region has an isoelectric point exceeding the second region's isoelectric point. The substrate is immersed in a solution of a bi-functional precursor having anchoring and charged ends. The anchoring end bonds to the first region to form a self-assembled monolayer having a charged end. The substrate with charged monolayer is immersed in a solution of carbon nanotubes having an opposite charge to form a carbon nanotube layer on the self-assembled monolayer. The charged carbon nanotubes are made by functionalization or coating with an ionic surfactant.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: February 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Hongsik Park, George S. Tulevski
  • Patent number: 9881791
    Abstract: Disclosed are a method for producing an oxide film using a low temperature process, an oxide film and an electronic device. The method for producing an oxide film according to an embodiment of the present invention includes the steps of coating a substrate with an oxide solution, and irradiating the oxide solution coat with ultraviolet rays under an inert gas atmosphere.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 30, 2018
    Assignees: KOREA ELECTRONICS TECHNOLOGY INSTITUTE, CHUNG-ANG UNIVERSITY INDUSTRY-ACADEMY COOPERATION FOUNDATION
    Inventors: Yong Hoon Kim, Sung Kyu Park, Min Suk Oh, Ji Wan Kim
  • Patent number: 9859250
    Abstract: The present invention discloses a substrate where the lateral surface of the substrate is formed to expose at least one portion of a via(s) for circuit connection. The substrate comprises a plurality of insulating layers; and a plurality of conductive layers separated by the plurality of insulating layers. A first lateral surface of the substrate is formed by the plurality of conductive layers and the plurality of insulating layers. The first lateral surface of the substrate comprises at least one first portion of a first via filled with a first conductive material.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: January 2, 2018
    Assignee: CYNTEC CO., LTD.
    Inventors: Bau-Ru Lu, Ming-Chia Wu, Shao Wei Lu
  • Patent number: 9859481
    Abstract: A light emitting device includes: a package equipped with a lead that has an upper surface and a lower surface, and has a metal board and a plating layer formed on a surface of the metal board, the plating layer including a first plating layer provided to an upper surface of the metal board, and a second plating layer provided to a lower surface of the metal board, the first plating layer including nickel plating layer, gold plating layer and silver plating layer, and the second plating layer including no nickel plating layer and gold plating layer, and a molded resin that holds the lead; a light emitting element mounted in the package; and a sealing member that seals the light emitting element.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: January 2, 2018
    Assignee: Nichia Corporation
    Inventor: Tomohide Miki
  • Patent number: 9859118
    Abstract: The present invention, when forming a pattern on a substrate, forms a film of a block copolymer containing at least two polymers on the substrate, heats the film of the block copolymer under a solvent vapor atmosphere to subject the block copolymer to phase separation, and removes one of the polymers in the film of the phase-separated block copolymer, thereby accelerating fluidization of the polymers of the block copolymer to enable acceleration of the phase separation.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: January 2, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Makoto Muramatsu, Takahiro Kitano, Tadatoshi Tomita, Keiji Tanouchi
  • Patent number: 9853001
    Abstract: A semiconductor chip includes a chip substrate; a self-destructive layer arranged on the chip substrate, the self-destructive layer including a pyrophoric reactant; and a sealant layer arranged on a surface of the self-destructive layer, on sidewalls of the self-destructive layer, and on the chip substrate such that the sealant layer forms a package seal on the semiconductor chip; wherein the pyrophoric reactant ignites spontaneously upon exposure to air.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: December 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 9831351
    Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: November 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki