Patents Examined by Molly K Reida
  • Patent number: 10916627
    Abstract: A semiconductor device includes a plurality of nano sheet stacks disposed above a substrate. Each nanosheet stack has a first nanosheet and a first sacrificial layer, the first nanosheet and the first sacrificial layer each include a first end and a second end. The first end and the second end of the first sacrificial layer are recessed from the first and second ends of the first nanosheet. Each nanosheet stack has a bottom sacrificial layer formed on top of the substrate. The bottom sacrificial layer has a first end and a second end, which are recessed from the first and second ends of the first nanosheet. The semiconductor also has a source or drain (S/D) structures formed in contact with the first end and the second end of the first nanosheet. The S/D structures are isolated from the substrate by the bottom sacrificial layer.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas Loubet, Pietro Montanini
  • Patent number: 10916662
    Abstract: An oxide thin film transistor, an array substrate, and preparation methods thereof are disclosed. The method for preparing an oxide thin film transistor comprises a step of forming a pattern comprising an oxide semiconductor active layer on a substrate, wherein the step comprises: forming an amorphous oxide semiconductor thin film on the substrate; performing an excimer laser annealing, at least at a position in the amorphous oxide semiconductor thin film corresponding to a channel region of oxide semiconductor active layer to be formed, such that the amorphous oxide semiconductor material at the laser-annealed position is crystallized, to form a crystalline oxide semiconductor material; and forming the pattern comprising the oxide semiconductor active layer.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: February 9, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Feng Guan, Guangcai Yuan, Zhi Wang, Chen Xu, Qi Yao, Zhanfeng Cao, Ce Ning, Woobong Lee, Lei Chen
  • Patent number: 10910357
    Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a first die, a second die and a hybrid bonding structure disposed between the first die and the second die. The first die includes a first front side and a first back side opposite to the first front side. The second die includes a second front side and a second back side opposite to the second front side. The hybrid bonding structure is disposed between the first back side of the first die and the second front side of the second die. The first die and the second die are bonded to each other by the hybrid bonding structure. The hybrid bonding structure includes an organic barrier layer and an inorganic barrier layer bonded to each other.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: February 2, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 10886441
    Abstract: Light emitting devices (LEDs) are described. An LED includes a light emitting semiconductor structure that includes a light emitting active layer disposed between an n-layer and a p-layer. A wavelength converting material may be disposed adjacent the light emitting semiconductor structure. The wavelength converting material includes multiple pores, at least one of which contains a second material. An absolute value of a ratio of a coefficient of thermal expansion of the second material to a coefficient of thermal expansion of the wavelength converting material is at least two in an embodiment, at least ten in another embodiment, at least 100 in another embodiment, and at least 1,000 in yet another embodiment.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: January 5, 2021
    Assignee: Lumileds LLC
    Inventors: Daniel Estrada, Marcel Rene Bohmer, Jacobus Johannes Francisus Gerardus Heuts, Kentaro Shimizu, Michael David Camras
  • Patent number: 10879369
    Abstract: A semiconductor device includes a fin extending from an upper surface of a substrate, a gate stack disposed over the fin, a first dielectric material disposed on a sidewall of the gate stack, an epitaxy region disposed adjacent the fin, a second dielectric material disposed on the epitaxy region and on a sidewall of the first dielectric material, wherein the second dielectric material has a greater thickness in a first portion over the epitaxy region than in a second portion over the epitaxy region disposed closer to the substrate than the first portion, a third dielectric material disposed on the second dielectric material, and a conductive feature extending through the third dielectric material and the second dielectric material to contact the epitaxy region.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiang-Wei Lin
  • Patent number: 10868032
    Abstract: In an example of forming a stacked memory array, a stack of alternating first and second dielectrics is formed. A dielectric extension is formed through the stack such that a first portion of the dielectric extension is in a first region of the stack between a first group of semiconductor structures and a second group of semiconductor structures in a second region of the stack and a second portion of the dielectric extension extends into a third region of the stack that does not include the first and second semiconductor structures. An opening is formed through the first region, while the dielectric extension couples the alternating first and second dielectrics in the third region to the alternating first and second dielectrics in the second region.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Yoshiaki Fukuzumi
  • Patent number: 10867809
    Abstract: A method of forming a semiconductor device includes forming a doped region on a semiconductor substrate, in which the doped region comprises an impurity therein, and performing a laser anneal process to the doped region with a process gas containing a dopant gas, in which the dopant gas and the impurity comprise the same chemical element.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: December 15, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chun-Ti Lu, Meng-Chin Lee, Fang-Liang Lu, Chee-Wee Liu
  • Patent number: 10861960
    Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shu Wu, Ying-Ya Hsu, Ching-Yu Pan, Hsiu-Hao Tsao, An Chyi Wei, Yuan-Hung Chiu
  • Patent number: 10863282
    Abstract: A MEMS package has a MEMS chip, a package substrate which the MEMS chip is adhered, a chip-cover which wraps the MEMS chip, and a cover-supporting part which supports the chip-cover from the inside. In the MEMS package, the chip-cover is supported by the cover-supporting part to form a back chamber, surrounded by the chip-cover and the package substrate.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: December 8, 2020
    Assignee: SAE Magnetics (H.K.) Ltd.
    Inventors: Koichi Shiozawa, Masashi Shiraishi, Jumpei Tsuchiya, Lik Hang Ken Wan, Toyotaka Kobayashi, Hironobu Hayashi
  • Patent number: 10854648
    Abstract: An image sensor includes a sensor layer and at least one metal layer. The sensor layer includes a plurality of sensing elements arranged as a 2-dimensional array along a first direction and a second direction. Each of the at least one metal layer includes a plurality of metal wires configured to form a plurality of apertures for passing lights to the plurality of sensing elements. At least one of the plurality of metal wires forming the plurality of apertures is disposed along a third direction different from the first direction and the second direction.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: December 1, 2020
    Assignee: NOVATEK Microelectronics Corp.
    Inventor: Chi-Ting Chen
  • Patent number: 10847603
    Abstract: In a capacitor of an integrated circuit, a crystallization induction film is obtained by oxidizing a surface of an electrode, and a dielectric structure is formed on the crystallization induction film, to reduce defect density generated in the dielectric film, improve leakage current, and reduce equivalent oxide thickness.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-min Moon, Su-hwan Kim, Hyun-jun Kim, Seong-yul Park, Young-lim Park, Jae-wan Chang
  • Patent number: 10847669
    Abstract: A photodetection element includes: a photoelectric conversion structure that contains a first material having an absorption coefficient higher than an absorption coefficient of monocrystalline silicon for light of a first wavelength, for which monocrystalline silicon exhibits absorption, and generates positive and negative charges by absorbing a photon; and an avalanche structure that includes a monocrystalline silicon layer, in which avalanche multiplication occurs as a result of injection of at least one selected from the group consisting of the positive and negative charges from the photoelectric conversion structure. The first material includes at least one selected from the group consisting of an organic semiconductor, a semiconductor-type carbon nanotube, and a semiconductor quantum dot.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: November 24, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Katsuya Nozawa
  • Patent number: 10847362
    Abstract: A method of fabricating a semiconductor device, the method including forming semiconductor patterns on a substrate such that the semiconductor patterns are vertically spaced apart from each other; and forming a metal work function pattern to fill a space between the semiconductor patterns, wherein forming the metal work function pattern includes performing an atomic layer deposition (ALD) process to form an alloy layer, and the ALD process includes providing a first precursor containing an organoaluminum compound on the substrate, and providing a second precursor containing a vanadium-halogen compound on the substrate.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyu-Hee Park, Yangsun Park, Jaesoon Lim, Younjoung Cho
  • Patent number: 10840153
    Abstract: A method includes providing a structure having a first region and a second region, the first region including a first channel region, the second region including a second channel region; forming a gate stack layer over the first and second regions; patterning the gate stack layer, thereby forming a first gate stack over the first channel region and a second gate stack over the second channel region; and laterally etching bottom portions of the first and second gate stacks by applying different etchant concentrations to the first and second regions simultaneously, thereby forming notches at the bottom portions of the first and second gate stacks.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10840386
    Abstract: A semiconductor apparatus has a semiconductor substrate, a first trench provided in a front surface of the semiconductor substrate, an anode electrode provided inside the first trench, and a cathode electrode provided on a back surface of the semiconductor substrate. The semiconductor substrate has a first p-type region, a second p-type region, and a main n-type region which is in contact with the first p-type region and the second p-type region, and is in Schottky contact with the anode electrode in the side surface of the first trench. The semiconductor substrate satisfies the relationship that an area of the first trench, when the front surface is viewed in a plan view, is smaller than an area of a Schottky interface where the main n-type region is in contact with the anode electrode in the side surface of the first trench.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: November 17, 2020
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hiroki Miyake, Yasushi Urakami, Yusuke Yamashita
  • Patent number: 10840135
    Abstract: Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 17, 2020
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10832969
    Abstract: Semiconductor devices and methods of forming the same include forming a dummy gate over a fin, which has a lower semiconductor layer, an insulating intermediate layer, and an upper semiconductor layer, to establish a channel region and source/drain regions. Source/drain extensions are grown on the lower semiconductor layer. Source/drain extensions are grown on the upper semiconductor layer. The dummy gate is replaced with a gate stack.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Miao, Choonghyun Lee, Shogo Mochizuki, Hemanth Jagannathan
  • Patent number: 10833130
    Abstract: A display device according to an embodiment of the present invention includes first and second electroluminescent elements on a substrate. The first and second electroluminescent elements each include a lower electrode, a functional layer including a light-emitting layer, an upper electrode, and a first or second color filter. The display device includes an overlapping region where the first and second color filters overlap each other in a plan view. Light transmitted through the first color filter has a higher luminosity factor than light transmitted through the second color filter. L2>L1, wherein L2 is the distance between the light-emitting region of the second electroluminescent element and the second color filter, and L1 is the distance between the light-emitting region of the first electroluminescent element and the first color filter.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 10, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koji Ishizuya, Tetsuo Takahashi
  • Patent number: 10825726
    Abstract: A method and structure of forming an interconnect structure with a sidewall image transfer process such as self-aligned double patterning to reduce capacitance and resistance. In these methods and structures, the spacer is a metal.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, James J. Kelly, Yann Mignot, Cornelius Brown Peethala, Lawrence A. Clevenger
  • Patent number: 10818579
    Abstract: There is provided a lead frame. The lead frame includes: a die pad; a lead terminal that is separated from the die pad and disposed around the die pad; and a resin layer that is formed between the die pad and the lead terminal so as to fix the die pad and the lead terminal. The resin layer has an opening portion that exposes at least a lower surface of the lead terminal.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 27, 2020
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Shintaro Hayashi, Kentaro Kaneko, Tsukasa Nakanishi, Misaki Imai