Patents Examined by Molly K Reida
  • Patent number: 11367691
    Abstract: An electronic semiconductor component with a housing structure and a cavity introduced into the housing structure is specified. The cavity comprises a base surface. Furthermore, the electronic semiconductor component comprises an auxiliary layer arranged on the base surface of the cavity and a marking penetrating the auxiliary layer at least as far as the base surface of the cavity. The marking comprises an optical contrast that depends on both an optical property of the housing structure and an optical property of the auxiliary layer. Furthermore, a method for producing an electronic semiconductor component is given.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 21, 2022
    Assignee: OSRAM OLED GmbH
    Inventors: Matthias Kiessling, Andreas Reith
  • Patent number: 11367814
    Abstract: An LED light-source substrate includes a first bonding sheet covering the LED, a second bonding sheet formed on the first bonding sheet, and a reflective layer formed on the second bonding sheet to suppress light from the LED. The second bonding sheet is bonded peelably from the first bonding sheet.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: June 21, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hisashi Watanabe, Takeshi Masuda, Hirotoshi Yasunaga, Youzou Kyoukane
  • Patent number: 11355510
    Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 7, 2022
    Assignee: Kioxia Corporation
    Inventors: Tetsuya Yamashita, Takuyo Nakayama, Takashi Ichikawa, Tadayoshi Uechi, Takashi Izumida
  • Patent number: 11342346
    Abstract: A semiconductor device including vertical structures on a substrate; and interlayer insulating layers and gate layers on the substrate, wherein the gate layers are sequentially stacked in a memory cell array area and extend into an extension area, the gate layers have pad regions having a staircase structure in the extension area, the first vertical structure has a surface facing the gate layers, the second vertical structure has a surface facing at least one of the gate layers, the first vertical structure includes a first core pattern, a first semiconductor layer, and a pad pattern, the second vertical structure includes a second core pattern and a second semiconductor layer, each of the core patterns includes an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junhyoung Kim, Jisung Cheon
  • Patent number: 11335717
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a light-collimating layer. The substrate has a plurality of pixels. The light-collimating layer is disposed on the substrate, and the light-collimating layer includes a transparent material layer, a first light-shielding layer, a second light-shielding layer and a plurality of transparent pillars. The transparent material layer covers the pixels. The first light-shielding layer is disposed on the substrate and the first light-shielding layer has a plurality of holes corresponding to the pixels. The second light-shielding layer is disposed on the first light-shielding layer. The transparent pillars are disposed in the second light-shielding layer.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 17, 2022
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Ren Lao, Chih-Cherng Liao, Shih-Hao Liu, Wu-Hsi Lu, Ming-Cheng Lo, Wei-Lun Chung, Chih-Wei Lin
  • Patent number: 11328962
    Abstract: A method includes providing a structure having a substrate and a fin protruding from the substrate, forming a gate stack layer over the fin, and patterning the gate stack layer in forming a gate stack. The patterning of the gate stack layer simultaneously forms a passivation layer on sidewall surfaces of the gate stack. The method also includes removing a bottom portion of the passivation layer, thereby exposing a bottom portion of the gate stack, while a top portion of the passivation layer remains. The method further includes laterally etching the bottom portion of the gate stack, thereby shrinking a width of the bottom portion of the gate stack.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
  • Patent number: 11322656
    Abstract: A semiconductor light emitting element includes: an n-type clad layer of an n-type aluminum gallium nitride (AlGaN)-based semiconductor material; an active layer of an AlGaN-based semiconductor material provided on a first top surface of the n-type clad layer; and an n-side electrode provided on a second top surface of the n-type clad layer adjacent to the first top surface. The n-side electrode includes a first metal layer on the second top surface containing titanium (Ti) and a second metal layer on the first metal layer containing aluminum (Al). A root-mean-square roughness (Rq) of a top surface of the second metal layer is 5 nm or less.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: May 3, 2022
    Assignee: NIKKISO CO., LTD.
    Inventors: Haruhito Sakai, Noritaka Niwa, Tetsuhiko Inazu
  • Patent number: 11296110
    Abstract: A nonvolatile memory device includes a mold structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate, a semiconductor pattern penetrating through the mold structure and contacting the substrate, a first charge storage film, and a second charge storage film separated from the first charge storage film. The first and second charge storage films are disposed between each of the gate electrodes and the semiconductor pattern. Each of the gate electrodes includes a first recess and a second recess which are respectively recessed inward from a side surface of the gate electrodes. The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Young Jung, Jong Won Kim, Young Hwan Son, Jee Hoon Han
  • Patent number: 11282987
    Abstract: A method of manufacturing a display device includes preparing a plurality of light-emitting element packages on a substrate, preparing a first solution including first semiconductor nanocrystals, applying a voltage to a part of the plurality of light-emitting element packages to transport the first semiconductor nanocrystals to a region overlapped with the part of the plurality of light-emitting element packages, and forming a first color conversion layer with the first semiconductor nanocrystals.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: March 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Deukseok Chung, Tae Gon Kim
  • Patent number: 11270939
    Abstract: A first conductive routing structure is electrically connected to a first electronic component. A second conductive routing structure is electrically connected to a second electronic component. An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure, which extends from a portion of the first conductive routing structure to a portion of the second conductive routing structure, to configure a circuit including the first and second electronic components.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: March 8, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Paul Merle Emerson, Benjamin Stassen Cook
  • Patent number: 11264334
    Abstract: The present disclosure provides a package device and a method of manufacturing the same. The package device includes a supporting member, a main component, a sealant, and a conductive encapsulant. The supporting member includes a plurality of grounding contacts. The main component is mounted on the supporting member. The sealant covers the main component. The conductive encapsulant encases the sealant and the grounding contacts exposed through the sealant for EMI shielding.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: March 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Han-Ning Pei
  • Patent number: 11239176
    Abstract: A package comprising a carrier, an electronic component mounted on the carrier, and an identifier indicative of an origin of the package and being formed on and/or in the carrier is disclosed.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: February 1, 2022
    Assignee: Infineon Technologies AG
    Inventors: Jochen Dangelmaier, Klaus Elian
  • Patent number: 11227866
    Abstract: A semiconductor device includes a substrate, a lower electrode provided over the substrate, a capacitive insulating film, and an upper electrode provided over the lower electrode, wherein the lower electrode has an upper portion and a lower portion, and at a boundary between the upper portion and the lower portion, the diameter of the upper portion is smaller than the diameter of the lower portion.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: January 18, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Akira Kaneko
  • Patent number: 11211263
    Abstract: Certain aspects of the present disclosure provide apparatus and techniques for partially molding packages for integrated circuits. A packaged assembly for integrated circuits includes: a substrate having at least one mold barrier between a first region on a first surface of the substrate and a second region on the first surface; a die attached to the substrate; one or more components attached to the substrate in the first region; and a first encapsulant over the one or more components in the first region, wherein the at least one mold barrier is configured to block a portion of the first encapsulant from moving from the first region of the substrate to the second region of the substrate during an application of the first encapsulant.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: December 28, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Srikanth Kulkarni, Rajneesh Kumar, Sayok Chattopadhyay
  • Patent number: 11211311
    Abstract: An electronic device has a sealing part 90, a first main terminal 11 protruding outward from the sealing part 90, a second main terminal 12 protruding outwardly from the sealing part, an electronic element 95 provided in the sealing part and having a front surface electrically connected to the first main terminal 11 and a back surface electrically connected to the second main terminal 12, a head part 40 connected to the front surface of the electronic element 95, a sensing terminal 13 protruding to an outside from the sealing part 90 and used for sensing and a connection part 35 integrally formed with the head part 40 and electrically connected to the sensing terminal 13. A current flowing through the sensing terminal 13 and the connection part 35 among a sensing current path does not overlap a main current path flowing through the second main terminal 12, the electronic element 95 and the first main terminal 11.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: December 28, 2021
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Soichiro Umeda, Yuji Morinaga
  • Patent number: 11201181
    Abstract: An image sensor includes a sensor layer and a metal layer. The sensor layer includes a plurality of sensing elements arranged as a 2-dimensional array along a first direction and a second direction. The metal layer includes a plurality of metal wires configured to form a plurality of apertures superposed on the plurality of sensing elements. At least one of the plurality of metal wires forming the plurality of apertures is entirely disposed along a third direction different from the first direction and the second direction.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: December 14, 2021
    Assignee: NOVATEK Microelectronics Corp.
    Inventor: Chi-Ting Chen
  • Patent number: 11195989
    Abstract: The present disclosure is to provide a ferromagnetic tunnel junction element and a method of manufacturing the ferromagnetic tunnel junction element capable of avoiding changes in the characteristics of the element and maintaining a high fabrication yield, while avoiding an increase in the area occupied by the element and an increase in the number of manufacturing steps. The ferromagnetic tunnel junction element to be provided includes: a first magnetic layer; a first insulating layer disposed on the first magnetic layer; a second magnetic layer containing a magnetic transition metal, the second magnetic layer being disposed on the first insulating layer; and a magnesium oxide film containing the magnetic transition metal, the magnesium oxide film being disposed to cover the side surfaces of the second magnetic layer.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: December 7, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Yutaka Higo, Hiroyuki Uchida, Naoki Hase, Yo Sato
  • Patent number: 11183534
    Abstract: This application describes a light emitting device or an assembly of light emitting devices, each with a small footprint. The light emitting device comprises two transistors, a capacitor, and an LED. The transistors comprise single crystal semiconductor. The capacitor is vertically-oriented. The LED overlies the transistors and capacitor. Methods to form the light emitting device or assembly are discussed.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 23, 2021
    Assignee: Black Peak LLC
    Inventor: Scott Brad Herner
  • Patent number: 11183612
    Abstract: The invention relates to a method for producing at least one optoelectronic component (100) comprising the steps A) providing an auxiliary carrier (1), B) epitaxially applying a sacrificial layer (2) on the auxiliary carrier (1), wherein the sacrificial layer (2) comprises germanium, C) epitaxially applying a semiconductor layer sequence (3) on the sacrificial layer (2), D) removing the sacrificial layer (2) by means of dry etching (9), such that the auxiliary carrier (1) is removed from the semiconductor layer sequence (3).
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: November 23, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Petrus Sundgren, Christoph Klemp
  • Patent number: 11183473
    Abstract: An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Chen-Hua Yu, Jing-Cheng Lin