Abstract: A chip package includes a semiconductor structure and a redistribution layer. The semiconductor structure has a substrate, a first isolation layer, and a lower ground pad. The substrate has a top surface, a bottom surface opposite to the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The first isolation layer is located on the top surface of the substrate, and the lower ground pad is located in the through hole. The redistribution layer extends from the bottom surface of the substrate to the lower ground pad along the sidewall. The redistribution layer covers the entire bottom surface of the substrate and electrically connects the lower ground pad.

Abstract: An imaging device according to an embodiment of the present disclosure includes: a first substrate including, in a first semiconductor substrate, a sensor pixel that performs photoelectric conversion; a second substrate including, in a second semiconductor substrate, a readout circuit that outputs a pixel signal based on electric charges outputted from the sensor pixel, the second substrate being stacked on the first substrate; a first insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; and a second insulating layer provided between the first semiconductor substrate and the second semiconductor substrate, and having lower film density than the first insulating layer.

Abstract: A semiconductor device includes an active region and a trapping region positioned peripherally with respect to the active region, the trapping region presenting trapping apertures permitting the passage of particles, the trapping apertures being in fluid communication with at least one trapping chamber for trapping the particles. A method for manufacturing the semiconductor devices from one semiconductor wafer presents semiconductor device regions to be singulated along a dicing portion line.

Abstract: A memory device may include an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers that are alternately stacked on a substrate; a trench in the electrode structure, and having an upper sidewall, a lower sidewall and a horizontal portion that couples the upper sidewall to the lower sidewall and that is parallel to a top surface of the substrate; a dielectric layer in the trench; and a slimming hole in the electrode structure having a sidewall of the trench and a region of the dielectric layer, and having a bottom surface disposed on an electrode layer on which the horizontal portion of the trench is positioned.

Abstract: A method for forming a memory includes: forming a bit line structure and a capacitor contact layer, where the bit line structure includes a bit line, a bit line cap layer and a bit line isolation layer, and the capacitor contact layer covers part of a side wall of the bit line isolation layer; forming a stop layer covering the side wall of the bit line isolation layer; forming a capacitor landing layer covering a top surface of the capacitor contact layer; and etching the bit line isolation layer by using the stop layer as an etch stop layer to form an air gap in the bit line isolation layer. Probability of occurrence of a short circuit between the capacitor landing layer and a bit line is reduced.

Abstract: A semiconductor structure includes: a transistor structure and a capacitor structure that are arranged along a first direction, where the capacitor structure extends along the first direction; and a wordline staircase structure extending along the first direction, where the wordline staircase structure and the transistor structure are disposed along a second direction intersecting with the first direction. A plane perpendicular to the second direction is used as a reference plane. An orthographic projection of the transistor structure on the reference plane is a first projection. An orthographic projection of the capacitor structure on the reference plane is a second projection. An orthographic projection of the wordline staircase structure on the reference plane is a third projection. The third projection covers the first projection, and the third projection partially overlaps the second projection.

Abstract: A semiconductor device includes a substrate, a lower electrode provided over the substrate, a capacitive insulating film, and an upper electrode provided over the lower electrode, wherein the lower electrode has an upper portion and a lower portion, and at a boundary between the upper portion and the lower portion, the diameter of the upper portion is smaller than the diameter of the lower portion.

Abstract: A light-emitting element contains negative ions and positive ions, and includes a solid ionic layer, a layer containing quantum dots, and a cathode electrode and an anode electrode. The ionic layer includes a p-type doped region on the anode electrode side containing the negative ions in a higher quantity than the positive ions, an n-type doped region on the cathode electrode side containing the positive ions in a higher quantity than the negative ions, and a junction region between the p-type doped region and the n-type doped region. The layer containing the quantum dots is adjacent to the junction region. Alternatively, the quantum dots are contained in the junction region. Alternatively, the quantum dots are adjacent to the junction region.

Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first, block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

Abstract: An imaging device includes a photoelectric converter that converts incident light to charge, a semiconductor substrate that includes an element isolation region and a first impurity region of a first conductivity type, the first impurity region being electrically connected to the photoelectric converter, a plug that includes a first semiconductor, the plug being connected directly to the first impurity region, a pad that includes a second semiconductor, the pad being connected directly to the plug, and a first transistor that includes the first impurity region as one of a source and a drain and includes a first gate. The first impurity region is positioned between the first gate and a first portion of the element isolation region in plan view. The pad overlaps the first gate and the first portion in plan view.

Abstract: A solid-state imaging device includes an imaging element array that includes M imaging elements arranged in a first direction and N imaging elements arranged in a second direction, that is, M×N imaging elements in total, each of the imaging elements including a photoelectric conversion unit that includes a photoelectric conversion layer 21, an insulation layer 32, a charge discharge electrode 22, an upper electrode 23, and a charge accumulation electrode 24. The photoelectric conversion layer is provided as a common layer at least for the N imaging elements. The photoelectric conversion unit of each of the imaging elements further includes a first charge transfer control electrode 25, a second charge transfer control electrode 26, and a light shielding layer 12. The photoelectric conversion layer 21 includes a photoelectric conversion layer-first region 21A, a photoelectric conversion layer-second region 21B, and a photoelectric conversion layer-third region 21C.

Abstract: A detection device includes a substrate, a plurality of photodiodes provided on the substrate, a plurality of transistors provided correspondingly to the respective photodiodes, a plurality of gate lines that extend in a first direction, a plurality of signal lines that extend in a second direction intersecting the first direction, a plurality of lower electrodes that are provided between the transistors and the photodiodes in a direction orthogonal to the substrate, and are provided correspondingly to the respective photodiodes, an upper electrode provided so as to extend across the photodiodes, and a reflective layer provided between the substrate and each of the photodiodes in the direction orthogonal to the substrate. Each of the lower electrodes has a smaller area than an area defined by the gate lines and the signal lines, and the reflective layer is provided between the lower electrodes adjacent to each other in a plan view.

Abstract: Disclosed are three-dimensional semiconductor memory devices, electronic systems including the same, and methods of fabricating the same. The three-dimensional semiconductor memory device includes a substrate including a cell array region and an extension region, a peripheral circuit structure including peripheral transistors on the substrate, a stack structure including interlayer dielectric layers and gate electrodes that are alternately stacked on the peripheral circuit structure, contacts that penetrate the stack structure on the extension region and are electrically connected with the peripheral transistors and include a protruding part contacting a sidewall of one of the gate electrodes and a vertical part penetrating the stack structure, and dielectric patterns between the vertical part and respective sidewalls of the gate electrodes. Top and bottom surfaces of each of the dielectric patterns are respectively in contact with adjacent ones of the interlayer dielectric layers.

Abstract: An integrated circuit semiconductor device includes a lower electrode formed on a substrate extending in a first direction and a second direction perpendicular to the first direction and a support structure supporting the lower electrode. The support structure includes a support pattern surrounding the lower electrode, extending in the first direction and the second direction, and having a hole through which the lower electrode passes, and a concavo-convex structure having at a surface of the support pattern a plurality of convex portions extending in a third direction perpendicular to the first direction and the second direction, and a plurality of concave portions arranged between the convex portions.

Abstract: An imaging device includes: a photoelectric conversion film; a first electrode located above the photoelectric conversion film; a second electrode; a plug coupled to the second electrode; a protective film located above the second electrode; and a wiring line that electrically couples the first electrode to the second electrode. The protective film overlaps the entire plug and does not overlap the photoelectric conversion film in plan view. The second electrode includes a non-overlapping portion that does not overlap the protective film in plan view, and the wiring line is coupled to the non-overlapping portion of the second electrode.

Abstract: A display panel includes a first display region and a second display region, and the second display region includes a transparent display region and a transition display region. Pixel circuits corresponding to light-emitting units of the transparent display region and the transition display region are located in the transition display region, and the pixel circuits located in the transition display region includes a first drive transistor. Along a direction perpendicular to the substrate, an overlapping region is located between the gate transmission structures and a lower electrode disposed on a side, close to the substrate, of a light-emitting unit of the transition display region located above the respective gate transmission structure, a shielding layer connected to a fixed potential is disposed in at least part of the overlapping region to shield from parasitic capacitance between the lower electrode and the gate transmission structure.

Abstract: The disclosure relates to the technical field of semiconductors, and to a memory, a semiconductor structure and a method for same. The method includes: providing a substrate, the substrate including a plurality of conductive contact plugs in array distribution and insulation layers separating the conductive contact plugs; and forming a plurality of capacitive layers stacked and distributed in a direction perpendicular to the substrate on a surface of the substrate, each of the capacitive layers including a plurality of capacitances distributed at intervals, and the capacitances being respectively connected to different conductive contact plugs. According to the method, the storage capacity of capacitances can be increased, and product yield can be enhanced.

Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

Abstract: An image sensor is provided. The image sensor includes a substrate and isolation structures disposed on the substrate. The isolation structures are electrically non-conductive and define pixel regions. The image sensor also includes electrodes disposed on the substrate and in direct contact with the isolation structures. The image sensor further includes an active layer disposed between the isolation structures. Moreover, the image sensor includes an encapsulation layer disposed over the active layer. The image sensor also includes a color filter layer disposed over the encapsulation layer.

Abstract: An organic light emitting diode which suppresses external light reflection while reducing loss of light generated in an organic light emitting layer is disclosed. An organic light emitting diode includes a substrate, an anode on the substrate, a bank on the anode and exposing a part of the anode to define an emission area, an organic light emitting layer on the emission area and the bank, a cathode on the organic light emitting layer, a plurality of light shielding patterns on the cathode and overlapping the bank, and a light loss inducing layer located on a same plane as the plurality of light shielding patterns and disposed between a pair of light shielding patterns from the plurality of light shielding patterns, the light loss inducing layer having has a same thickness as a thickness of that of the plurality of light shielding patterns, and overlaps the emission area.