Patents Examined by Molly K Reida
  • Patent number: 10763355
    Abstract: A semiconductor device may include: a semiconductor layer; and a trench gate. The semiconductor layer may include: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type provided above the first semiconductor region and facing a side surface of the trench gate; and a third semiconductor region of the first conductive type provided above the second semiconductor region, separated from the first semiconductor region by the second semiconductor region, and facing the side surface of the trench gate. The first semiconductor region may include: a lower semiconductor region; and an upper semiconductor region disposed between the lower semiconductor region and the second semiconductor region and having a lower impurity concentration than the lower semiconductor region. The upper semiconductor region may be disposed at a shallower position than the trench gate and face the side surface of the trench gate.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 1, 2020
    Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventors: Tsutomu Uesugi, Masakazu Kanechika
  • Patent number: 10763429
    Abstract: Embodiments of the present invention are directed to a method for fabricating a magnetoresistive random access memory (MRAM) device. A non-limiting example of the method includes depositing a dielectric layer on a contact arranged on a substrate including a magnetic tunnel junction (MTJ) pillar. The method includes reducing a width of the MTJ pillar. The method further includes depositing an encapsulation layer on the dielectric layer and the MTJ pillar.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: September 1, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steve Holmes, Bruce B. Doris, Hyun K. Lee
  • Patent number: 10756242
    Abstract: A system and methods for light-emitting diode (LED) devices with a dimming feature that can tailor a color point shift in the light color temperature of a scattering/transparent layer to enlarge a dim to warm range are disclosed herein. A light-emitting device may include a wavelength converting structure configured to receive light from a light emitting semiconductor structure and an adjacent light scattering structure. The light scattering structure may comprise a plurality of scattering particles with a lower refractive index (RI) than the RI of the matrix material in which the scattering particles are disposed. The wavelength converting structure may include a red phosphor and a green phosphor such that to adjust overlap between green emission and absorption by the red phosphor to correspondingly adjust scattering and magnitude of color shift. In an embodiment, the light scattering structure may be integrated in the wavelength converting structure.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 25, 2020
    Assignee: LUMILEDS LLC
    Inventors: Daniel Estrada, Marcel Rene Bohmer, Jacobus Johannes Francisus Gerardus Heuts, Kentaro Shimizu, Michael David Camras
  • Patent number: 10756104
    Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: August 25, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
  • Patent number: 10749020
    Abstract: The invention relates to the group III-nitride semiconductor device and corresponding fabricating method. Specifically, a method to reduce RF dispersion in a group III-nitride high electron mobility transistor (HEMT), especially for reduced barrier thickness epi materials and scaled deices for higher frequency applications. Periodic n-type doping within barrier is used to screen surface state traps, which are responsible for the above-mentioned RF dispersion, without introducing additional gate leakage current path. Within the method, the barrier (typically AlGaN, AlInN) layer is periodically n-type doped with its composition (such as Al % within AlGaN) periodically modulated. The periodic structure is effective in both screening surface state traps and reducing the leakage current within the AlGaN/gate Schottky barrier.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: August 18, 2020
    Assignee: SUZHOU HAN HUA SEMICONDUCTOR CO., LTD.
    Inventors: Xian-Feng Ni, Qian Fan, Wei He
  • Patent number: 10749010
    Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method further includes recessing the fin structure to form a recess and implanting dopants from the recess to form a doped region. The method further includes diffusing the dopants in the doped region to form an expanded doped region and forming a source/drain structure over the expanded doped region.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Chun-Hsiung Tsai, Cheng-Yi Peng, Shih-Chieh Chang, Kuo-Feng Yu
  • Patent number: 10741674
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-treatment process. In an embodiment, a method includes subjecting a substrate surface having at least one feature to a film deposition process to form a conformal film over a bottom surface and along sidewall surfaces of the feature, subjecting the substrate surface to a treatment process to form respective halogen surface layers or respective halogen-terminated layers on the conformal film formed at respective upper portions of the sidewall surfaces, and performing sequentially and repeatedly the film deposition process and the treatment process to fill the feature with the film.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Pin-Ju Liang, I-Chen Yang
  • Patent number: 10734490
    Abstract: BJT devices with 3D wrap around emitter are provided. In one aspect, a method of forming a BJT device includes: forming a substrate including a first doped layer having a dopant concentration of from about 1×1020 at. % to about 5×1020 at. % and ranges therebetween, and a second doped layer having a dopant concentration of from about 1×1015 at. % to about 1×1018 at. % and ranges therebetween, wherein the first and second doped layers form a collector; patterning a fin(s) in the substrate; forming bottom spacers at a bottom of the fin(s); forming a base(s) that wraps around the fin(s); forming an emitter(s) that wraps around the base(s); and forming sidewall spacers alongside the emitter(s). A BJT device is also provided.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Injo Ok, Shogo Mochizuki, Soon-Cheon Seo
  • Patent number: 10734320
    Abstract: A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ravi Keshav Joshi, Rainer Pelzer, Axel Buerke, Sven Schmidbauer, Michael Nelhiebel
  • Patent number: 10727267
    Abstract: A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: July 28, 2020
    Assignee: Sensors Unlimited, Inc.
    Inventors: Wei Zhang, Douglas Stewart Malchow, Michael J. Evans, Wei Huang, Paul L. Bereznycky, Namwoong Paik
  • Patent number: 10727184
    Abstract: Described are example microelectronic devices including structures, such as build-up layers, formed of a non-homogeneous photoimageable dielectric material. The non-homogeneous photoimageable dielectric material includes two regions forming opposite surfaces of the material. A first region includes a first carbon content, and a second region located above the first region includes a second carbon content which is greater than that of the first region. The second region of the photoimageable dielectric material provides enhanced adhesion with metal that may be deposited above the material, such as a sputtered metal seed layer to facilitate subsequent deposition of an electroless metal over the non-homogeneous photoimageable dielectric material.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Siddharth K. Alur, Srinivas V. Pietambaram
  • Patent number: 10720507
    Abstract: A semiconductor device includes a fin extending from an upper surface of a substrate, a gate stack disposed over the fin, a first dielectric material disposed on a sidewall of the gate stack, an epitaxy region disposed adjacent the fin, a second dielectric material disposed on the epitaxy region and on a sidewall of the first dielectric material, wherein the second dielectric material has a greater thickness in a first portion over the epitaxy region than in a second portion over the epitaxy region disposed closer to the substrate than the first portion, a third dielectric material disposed on the second dielectric material, and a conductive feature extending through the third dielectric material and the second dielectric material to contact the epitaxy region.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiang-Wei Lin
  • Patent number: 10720509
    Abstract: The present application discloses a method for preparing a semiconductor device structure. The method includes: forming a ring structure over a substrate; performing an etching process to form an annular semiconductor fin under the ring structure; forming a processed area on a top portion of the substrate exposed by the annular semiconductor fin; selectively forming a spacer on a side surface of the annular semiconductor fin; forming a lower source/drain region on the surface of the substrate in contact with a bottom portion of the annular semiconductor fin; forming an inner gate structure in contact with an inner sidewall of the annular semiconductor fin and forming an outer gate structure in contact with an outer sidewall of the annular semiconductor fin; and forming an upper source/drain region on an upper portion of the annular semiconductor fin.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 21, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Cheng Liao
  • Patent number: 10714440
    Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Kim, Kyung Moon Jung, Seok Hwan Kim, Kyung Ho Lee, Kang Heon Hur
  • Patent number: 10700107
    Abstract: It is provided a low-temperature polysilicon thin film transistor formed on a substrate, including: a gate electrode on the substrate; an active layer on the gate electrode, the active layer including a channel region, the channel region having a polysilicon region and amorphous silicon regions respectively on both sides of the polysilicon region; and an etch stop layer on the active layer. An orthogonal projection of the polysilicon region on the substrate is located within an orthogonal projection of the gate electrode on the substrate, and an area of the orthogonal projection the polysilicon region on the substrate is smaller than an area of the orthogonal projection of the gate electrode on the substrate. The orthogonal projection of the polysilicon region on the substrate is located within an orthogonal projection of the etch stop layer on the substrate.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 30, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaolong He, Zhifu Li, Guangcai Yuan, Haijiao Qian, Dongsheng Li
  • Patent number: 10692990
    Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
  • Patent number: 10658498
    Abstract: A semiconductor device may include a semiconductor substrate, an upper electrode and a lower electrode. The semiconductor substrate may include: a p-type anode region being in contact with the upper electrode; an n-type cathode region being in contact with the lower electrode; an n-type drift region interposed between the anode region and the cathode region. The semiconductor substrate may further include a barrier region interposed between the anode region and the drift region; and an n-type pillar region extending between the barrier region and the upper electrode. The barrier region may include a multi-layer structure in which a p-type second barrier layer is interposed between an n-type first barrier layer and an n-type third barrier layer. The first barrier layer may be in contact with the anode region and is connected to the upper electrode via the pillar region.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: May 19, 2020
    Assignee: DENSO CORPORATION
    Inventor: Yasuhiro Hirabayashi
  • Patent number: 10651039
    Abstract: A method of forming a semiconductor device includes forming source regions and drain regions in a semiconductor substrate, and a gate electrode over said semiconductor substrate and between said source and drain regions. The gate electrode is formed from a first semiconductor gate electrode layer deposited on said gate dielectric layer at a first substrate temperature. A second semiconductor gate electrode layer is deposited on the first semiconductor gate electrode layer at a second substrate temperature greater than said first temperature. The two gate electrode layers may be annealed to form a homogenous polycrystalline layer with improved grain size distribution, thereby improving transistor matching in a semiconductor device.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 12, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pushpa Mahalingam, Umamaheswari Aghoram
  • Patent number: 10651046
    Abstract: Methods of self-aligned multiple patterning. A mandrel is formed over a hardmask, and a planarizing layer is formed over the mandrel and the hardmask. The planarizing layer is patterned to form first and second trenches exposing respective first and second lengthwise sections of the mandrel. A portion of the patterned planarizing layer covers a third lengthwise section of the mandrel arranged between the first and second lengthwise sections of the mandrel. After patterning the planarizing layer, the first and second lengthwise sections of the mandrel are removed with an etching process to define a pattern including a mandrel line exposing respective first portions of the hardmask. The third lengthwise section of the mandrel is masked by the portion of the planarizing layer during the etching process, and the third lengthwise section covers a second portion of the hardmask arranged along the mandrel line between the first portions of the hardmask.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hsueh-Chung Chen, Brendan O'Brien, Martin O'Toole, Keith Donegan
  • Patent number: 10644030
    Abstract: An integrated circuit includes a substrate and a plurality of standard cells. The standard cells are formed on the substrate, wherein each standard cell comprises a first fin, a second fin and a third fin, the second fin is located between the first fin and the third fin, and there is a first interval between the first fin and the second fin is different from a second interval between the first fin and the third fin.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 5, 2020
    Assignee: MEDIATEK INC.
    Inventors: Chuan-Shian Fu, Cheng-Jyi Chang, Shao-Hwang Sher