Patents Examined by Monica D. Harrison
  • Patent number: 10446409
    Abstract: An interlayer insulating film is dry etched using a CHF3 gas and by using, as a mask, a resist film having a first opening and a second opening that is wider than the first opening, thereby forming a first contact hole of a predetermined depth in the first opening and forming a second contact hole in the second opening. The gas in a furnace is switched to a C4F8 gas and the first contact hole is embedded with a polymer by the C4F8 gas. The gas in the furnace is switched to a CHF3 gas. With the first contact hole protected by the polymer, the interlayer insulating film is dry etched using the same resist film as a mask, making a depth of the second contact hole a predetermined depth deeper than that of the first contact hole. Thereafter, the resist film and the polymer are removed.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 15, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki Kuneshita
  • Patent number: 10439139
    Abstract: Provided are a laminate which includes an organic semiconductor film, a water-soluble resin layer, and a photosensitive resin layer and in which cracks are unlikely to occur; and a kit. The laminate includes a water-soluble resin layer containing a water-soluble resin and a photosensitive resin layer containing a photosensitive resin, which are provided in this order on an organic semiconductor film. The water-soluble resin layer and the photosensitive resin layer are adjacent to each other, the water-soluble resin is at least one of polyvinylpyrrolidone having a weight-average molecular weight of 300,000 or greater or polyvinyl alcohol having a weight-average molecular weight of 15,000 or greater, and the photosensitive resin has a weight-average molecular weight of 30,000 or greater.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: October 8, 2019
    Assignee: FUJIFILM Corporation
    Inventors: Seiya Masuda, Yoshitaka Kamochi, Atsushi Nakamura
  • Patent number: 10439016
    Abstract: An array substrate includes: a substrate; a first metal layer, disposed on the substrate, the first metal layer forming a gate electrode, a scan line and a first electrode, the scan line extending along a first direction in a plane of a surface of the substrate; a first insulation layer, disposed on the first metal layer; a second metal layer, disposed on the first insulation layer, the second metal layer forming a second electrode, projections of the first electrode and the second electrode on the substrate at least partly overlapping one another; a second insulation layer, disposed on the second metal layer; and a third metal layer, disposed on a side of the second insulation layer away from the second metal layer, the third metal layer forming an initialization signal line.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 8, 2019
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventor: Jui Ting Ho
  • Patent number: 10431152
    Abstract: A top-emission organic light-emitting display device includes a plurality of pixels each having color filters. Each of the plurality of pixels comprises a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged sequentially in a column direction. Each of the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel is extended in a row direction rather than in the column direction.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: October 1, 2019
    Assignee: LG Display Co., Ltd.
    Inventor: KyungMan Kim
  • Patent number: 10431564
    Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a chip package over a printed circuit board and multiple conductive bumps between the chip package and the printed circuit board. The chip package structure also includes one or more thermal conductive elements between the chip package and the printed circuit board. The thermal conductive element has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: October 1, 2019
    Assignee: MediaTek Inc.
    Inventor: Tzu-Hung Lin
  • Patent number: 10424601
    Abstract: An array substrate comprising: a plurality of scanning lines (G) arranged in a first direction; a plurality of data lines (S) arranged in a second direction, wherein said scanning lines (G) and said data lines (S) intersect and insulate, a plurality of defined array areas intersected by said scanning lines (G) and by said data lines (S) are a plurality of sub-pixels, wherein the sub-pixel corresponding to the data line is a sub-pixel column, and the sub-pixel corresponding to the scanning line is a sub-pixel row; and a plurality of data lines (S) are divided into a plurality of data line groups 10 arranged in the second direction, wherein each data line group 10 comprises six data line pairs, and data lines in one data line pair connect each other; there are at least four data line pairs corresponding to the same color sub-pixel column in one said data line group, and said sub-pixels comprise at least three colors.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 24, 2019
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yu-Jen Chen
  • Patent number: 10424631
    Abstract: A display device includes a substrate including a bending area located between a first area and a second area. The substrate is bent in relation to a bending axis. A first wiring unit including a plurality of first wirings is arranged on the substrate to sequentially extend over the first area, the bending area, and the second area. First central axes included in each of the plurality of first wirings are spaced apart from each other by a first pitch in the bending area. A second wiring unit including a plurality of second wirings is arranged on the substrate to sequentially extend over the first area, the bending area, and the second area. Second central axes included in each of the plurality of second wirings are spaced apart from each other by a second pitch greater than the first pitch in the bending area.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: September 24, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yangwan Kim, Sunja Kwon, Byungsun Kim, Hyunae Park, Sujin Lee, Jaeyong Lee
  • Patent number: 10403700
    Abstract: A display device includes a driving transistor and an organic EL element. The driving transistor includes an oxide semiconductor layer; a first gate electrode that region overlapping the oxide semiconductor layer; a first insulting layer between the first gate electrode and the oxide semiconductor layer; a second gate electrode that includes a region overlapping the oxide semiconductor layer and the first gate electrode; a second insulating layer between the second gate electrode and the oxide semiconductor layer; and a first and a second transparent conductive layer that are provided between the oxide semiconductor layer and the first insulating layer and each include a region contacting the oxide semiconductor layer. The organic EL element includes a first electrode; a second electrode; a light emitting layer between the first electrode and the second electrode; and an electron transfer layer between the light emitting layer and the first electrode.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: September 3, 2019
    Assignee: MIKUNI ELECTRON CORPORATION
    Inventor: Sakae Tanaka
  • Patent number: 10396193
    Abstract: An III-nitride HEMT, including a substrate; a semiconductor epitaxial stack, formed on the substrate, including a buffer structure, a channel layer formed on the buffer structure and a barrier layer formed on the channel layer, wherein a two-dimensional electron gas is formed between the channel layer and the barrier layer; and a first electrode, a third electrode and a second electrode located in between, respectively formed on the barrier layer, wherein the semiconductor epitaxial stack includes a sheet resistance greater than 500 ?/sq, wherein there is a first minimum space between the first electrode and the second electrode, a second minimum space between the second electrode and the third electrode, and the ratio of the first minimum space to the sum of first minimum space and the second minimum space is between 0.77 and 1, wherein the second electrode includes a length greater than or equal to 9 ?m.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: August 27, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chien-Kai Tung, Tien Ching Feng
  • Patent number: 10388538
    Abstract: An object of the present invention to provide a highly reliable semiconductor device. Another object is to provide a manufacturing method of a highly reliable semiconductor device. Still another object is to provide a semiconductor device having low power consumption. Yet another object is to provide a manufacturing method of a semiconductor device having low power consumption. Furthermore, another object is to provide a semiconductor device which can be manufactured with high mass productivity. Another object is to provide a manufacturing method of a semiconductor device which can be manufactured with high mass productivity. An impurity remaining in an oxide semiconductor layer is removed so that the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after adding a halogen element into the oxide semiconductor layer, heat treatment is performed to remove an impurity from the oxide semiconductor layer. The halogen element is preferably fluorine.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideyuki Kishida
  • Patent number: 10388733
    Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros
  • Patent number: 10388748
    Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: August 20, 2019
    Assignee: Acorn Technologies, Inc.
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 10381468
    Abstract: A semiconductor device includes a single electron transistor (SET) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10380956
    Abstract: An information terminal capable of switching display and non-display of images by strain. The information terminal includes a display portion and a strain sensor. The display portion includes a liquid crystal element, a light-emitting element, and a first and a second transistors. The strain sensor includes a strain sensor element and a resistor. The first transistor has a function of controlling current flowing into the light-emitting element. The strain sensor element has a function as a variable resistor. A first terminal of the strain sensor element is electrically connected to a first terminal of the resistor. A gate of the first transistor is electrically connected to a first terminal of the strain sensor element via the second transistor.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 13, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yuki Okamoto
  • Patent number: 10374079
    Abstract: A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: August 6, 2019
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirotaka Saikaku, Jun Sakakibara, Shoji Mizuno, Yuichi Takeuchi
  • Patent number: 10367075
    Abstract: A method of restricting diffusion of miscible materials across a barrier, including, forming a 2-dimensional material on a substrate surface, wherein the 2-dimensional material includes one or more defects through which a portion of the substrate surface is exposed, forming a plug selectively on the exposed substrate surface, and forming a cover layer on the plug and 2-dimensional material, wherein the cover layer material is miscible in the substrate material.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Priscilla D. Antunez, Damon B. Farmer
  • Patent number: 10366907
    Abstract: There is provided a manufacturing method of a semiconductor package in which plural semiconductor chips different in the thickness are mounted. In the manufacturing method, the back surface of a package board in which the plural semiconductor chips on a wiring base are collectively sealed by a sealant is held by a holding tape and a resin layer is thinned by a shaping abrasive stone. Then, a dividing unit is caused to cut to the middle of the holding tape along planned dividing lines to divide the package board into individual semiconductor packages.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 30, 2019
    Assignee: Disco Corporation
    Inventors: Byeongdeck Jang, Youngsuk Kim
  • Patent number: 10361121
    Abstract: Embodiments herein relate to a package using aluminum oxide as an adhesion and high-thermal conductivity layer with a buildup layer having a first side and a second side opposite the first side, a first trace applied to the first side of the buildup layer, an aluminum oxide layer coupled with the first trace and an exposed area of the first side of the buildup layer, a lamination buildup layer coupled with the aluminum oxide layer on a side of the aluminum oxide layer opposite the buildup layer, wherein the lamination buildup layer includes one or more vias to the trace, and a seed layer coupled with the lamination buildup layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Sri Ranga Sai Boyapati
  • Patent number: 10355126
    Abstract: A method for manufacturing a semiconductor device includes: forming a recess in a semiconductor substrate, the recess having a bottom and a sidewall extending from the bottom to a first side of the semiconductor substrate; forming an auxiliary structure on the sidewall and the bottom of the recess and forming a hollow space within the recess; filling the hollow space with a filling material; forming a plug on the first side of the semiconductor substrate to cover the auxiliary structure at least on the sidewall of the recess; forming an opening in the plug to partially expose the auxiliary structure in the recess; removing the auxiliary structure at least partially from the sidewall of the recess to form cavities between the auxiliary structure and the sidewall; and sealing the opening in the plug.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Oliver Blank
  • Patent number: 10347760
    Abstract: A reconfigurable field effect transistor (RFET) includes a nanowire, wherein the nanowire comprises two Schottky contacts, as well as two gate contacts partially enclosing the nanowire in cross section. An integrated circuit can be produced therefrom. The aim of producing CMOS circuits with enhanced functionality and a more compact design is achieved in that the nanowire is divided along the cross section thereof into two nanowire parts, wherein each nanowire part comprises a respective Schottky contact and a respective gate contact, and the two nanowire parts are connected electrically to one another via a common substrate and stand vertically on the substrate. In a nanowire-parts-array, between the nanowire parts, a respective top-gate contact and/or back-gate contact can be formed in a substrate defining a substrate plane.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 9, 2019
    Assignees: Technische Universität Dresden, NaMLab gGmbH
    Inventors: Tim Baldauf, André Heinzig, Walter Michael Weber