Patents Examined by Monica D. Harrison
  • Patent number: 12009324
    Abstract: A semiconductor structure and a forming method thereof are provided. The method of forming the semiconductor structure includes: providing a wafer having a front surface and a back surface opposite to the front surface; patterning the back surface of the wafer to form a groove extending from the back surface towards the front surface; forming a dielectric layer at a bottom and a side wall of the groove; and forming, on the dielectric layer, a conductive layer filling the groove.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: June 11, 2024
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Ping-Heng Wu
  • Patent number: 12007636
    Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: June 11, 2024
    Assignees: Japan Display Inc., Pansonic Liquid Crystal Display Co., Ltd.
    Inventors: Hideo Tanabe, Masaru Takabatake, Toshiki Kaneko, Atsushi Hasegawa, Hiroko Sehata
  • Patent number: 12002810
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up approach, are described. For example, integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of nanowires than the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 4, 2024
    Assignee: Intel Corporation
    Inventors: Dax M. Crum, Biswajeet Guha, Leonard Guler, Tahir Ghani
  • Patent number: 12004346
    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising a vertically alternating sequence of insulative structures and additional insulative structures, at least some of the additional insulative structures comprising silicon nitride having a ratio of nitrogen atoms to silicon atoms greater than about 1.58:1.00, forming openings through the stack structure, and forming cell pillar structures within the openings, the cell pillar structures individually comprising a semiconductor channel material vertically extending through the stack structure. Related methods, microelectronic devices, memory devices, and electronic systems are also described.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: June 4, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Swapnil Lengade, Jeremy Adams, Naiming Liu, Jeslin J. Wu, Kadir Abdul, Carlo Mendoza Orofeo
  • Patent number: 11996399
    Abstract: A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Szu-Ying Chen, Dun-Nian Yaung
  • Patent number: 11996472
    Abstract: A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.
    Type: Grant
    Filed: February 9, 2023
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ya-Yi Tsai, Chi-Hsiang Chang, Shih-Yao Lin, Tzu-Chung Wang, Shu-Yuan Ku
  • Patent number: 11996388
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 28, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11990526
    Abstract: A semiconductor device includes; an active region extending in a first horizontal direction on a substrate, source/drain regions disposed on the active region, a buried trench formed between the source/drain regions, a buried insulating layer surrounding both side walls of the buried trench in the first horizontal direction between the source/drain regions, a wing trench formed in a lower part of the buried trench and having a width greater than a width of the buried trench, and a gate electrode extending in a second horizontal direction on the active region, and disposed within each of the buried trench and the wing trench.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: May 21, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Mok Kim, Yong Sang Jeong, Kyung Lyong Kang, Jun Gu Kang
  • Patent number: 11990359
    Abstract: According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: (a) heating a substrate retainer in a reaction chamber, wherein the substrate retainer is provided with a plurality of slots capable of accommodating a plurality of substrates in a multistage manner; (b) repeatedly performing a set including: (b-1) moving the substrate retainer so as to locate one or more of the slots outside the reaction chamber; and (b-2) charging one or more of the substrates into the one or more of the slots; and (c) moving the substrate retainer such that the plurality of substrates charged in the plurality of slots are accommodated in the reaction chamber.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: May 21, 2024
    Assignee: Kokusai Electric Corporation
    Inventors: Takatomo Yamaguchi, Hidenari Yoshida, Kenji Ono
  • Patent number: 11987874
    Abstract: Implementations of methods of forming a metal layer on a semiconductor wafer may include: placing a semiconductor wafer into an evaporator dome and adding a material to a crucible located a predetermined distance from the semiconductor wafer. The semiconductor wafer may include an average thickness of less than 39 microns. The method may also include heating the material in the crucible to a vapor and depositing the material on a second side of the semiconductor wafer.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: May 21, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 11990331
    Abstract: A method for forming a silicon dioxide film and a method for forming a metal gate are provided. The method for forming a silicon dioxide film includes: forming a silicon dioxide layer on a semiconductor substrate, performing a nitrogen treatment to the silicon dioxide layer to convert the silicon dioxide layer of partial thickness into a mixed layer of silicon nitride and silicon oxynitride; and removing the mixed layer to form a silicon dioxide film on the semiconductor substrate.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: May 21, 2024
    Assignee: Changxin Memory Technologies, Inc.
    Inventors: Jingwen Lu, Wei Feng, Bingyu Zhu
  • Patent number: 11984474
    Abstract: There is disclosed a structure in a wide band gap material such as silicon carbide wherein there is a buried grid and shields covering at least one middle point between two adjacent parts of the buried grid, when viewed from above. Advantages of the invention include easy manufacture without extra lithographic steps compared with standard manufacturing process, an improved trade-off between the current conduction and voltage blocking characteristics of a JBSD comprising the structure.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: May 14, 2024
    Assignee: II-VI ADVANCED MATERIALS, LLC
    Inventor: Hossein Elahipanah
  • Patent number: 11984398
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure comprises: providing a substrate, comprising a polysilicon layer, a first conductive layer, a first dielectric layer, a mask layer, and a sacrificial layer sequentially formed thereon, wherein the sacrificial layer has a plurality of first trenches distributed at intervals; forming a first insulating layer on the sacrificial layer; forming a protective layer, the protective layer only covering a surface of the first insulating layer above the top surface of the sacrificial layer; removing the protective layer, part of the first insulating layer, the sacrificial layer, and part of the mask layer to form a first pattern layer; and removing part of the first dielectric layer, part of the first conductive layer, and part of the polysilicon layer by using the first pattern layer as a mask to form a BL structure.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: May 14, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yexiao Yu, Zhongming Liu, Jia Fang
  • Patent number: 11978789
    Abstract: Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: May 7, 2024
    Assignee: HRL LABORATORIES, LLC
    Inventor: Biqin Huang
  • Patent number: 11973142
    Abstract: An integrated circuit includes transistors respectively including channel layers in a substrate, source electrodes and drain electrodes respectively contacting both sides of the channel layers, gate electrodes on the channel layers, and ferroelectrics layers between the channel layers and the gate electrodes. Electrical characteristics of the ferroelectrics layers of at least two of the transistors are different. Accordingly, threshold voltages of the transistors are different from each other.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: April 30, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangwook Kim, Yunseong Lee, Sanghyun Jo, Jinseong Heo
  • Patent number: 11967524
    Abstract: Exemplary methods of forming a semiconductor structure may include forming a first silicon oxide layer overlying a semiconductor substrate. The methods may include forming a first silicon layer overlying the first silicon oxide layer. The methods may include forming a silicon nitride layer overlying the first silicon layer. The methods may include forming a second silicon layer overlying the silicon nitride layer. The methods may include forming a second silicon oxide layer overlying the second silicon layer. The methods may include removing the silicon nitride layer. The methods may include removing the first silicon layer and the second silicon layer. The methods may include forming a metal layer between and contacting each of the first silicon oxide layer and the second silicon oxide layer.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: April 23, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Praket Prakash Jha, Shuchi Sunil Ojha, Jingmei Liang, Abhijit Basu Mallick, Shankar Venkataraman
  • Patent number: 11967520
    Abstract: A method for making a high-voltage thick gate oxide, which includes depositing a pad silicon oxide on a silicon substrate and depositing a pad silicon nitride on the pad silicon oxide; performing shallow trench isolation photolithography, etching, silicon oxide filling and chemical mechanical polishing; sequentially depositing a mask silicon nitride and a mask silicon oxide on a silicon wafer; removing the mask silicon oxide and the mask silicon nitride in a high-voltage thick gate oxide region, and remaining the pad silicon nitride between two shallow trench isolations in the high-voltage thick gate oxide region; performing first thermal oxidation growth; removing the pad silicon nitride between the two shallow trench isolations in the high-voltage thick gate oxide region; performing second thermal oxidation growth to produce a high-voltage thick gate oxide.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: April 23, 2024
    Assignee: Hua Hong Semiconductor (Wuxi) Limited
    Inventor: Junwen Liu
  • Patent number: 11967526
    Abstract: A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region adjacent to the gate structure. A top of the dielectric cap is oxidized. After oxidizing the top of the dielectric cap, an etch stop layer is deposited over the dielectric cap and an interlayer dielectric (ILD) layer over the etch stop layer. The ILD layer and the etch stop layer are etched to form a via opening extending though the ILD layer and the etch stop layer. A source/drain via is filled in the via opening.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Te-Chih Hsiung, Peng Wang, Jyun-De Wu, Huan-Just Lin
  • Patent number: 11967503
    Abstract: Provided are a method of depositing a thin film and a method of manufacturing a semiconductor device using the same, and the method of depositing a thin film uses a substrate processing apparatus including a chamber, a substrate support on which a substrate is mounted, a gas supply unit, and a power supply unit that supplies high-frequency and low-frequency power to the chamber, and includes: a step of mounting, on the substrate support, the substrate including a lower thin film deposited under the condition of a process temperature in a low temperature range; a step of depositing an upper thin film on the lower thin film under the condition of the process temperature in the low temperature range; and a step of treating a surface of the upper thin film under the condition of the process temperature in the low temperature range.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: April 23, 2024
    Assignee: WONIK IPS CO., LTD.
    Inventors: Su In Kim, Young Chul Choi, Chang Hak Shin, Min Woo Park, Ji Hyun Kim, Kyung Mi Kim
  • Patent number: 11967651
    Abstract: A silicon carbide power diode device has a silicon carbide substrate on which a silicon carbide epitaxial layer with an active region is provided. A Schottky metal layer is on the active region, and a first electrode layer is on the Schottky metal layer. A first ohmic contact is on the silicon carbide substrate, and a second electrode layer is on the first ohmic contact. The active region of the silicon carbide epitaxial layer has a plurality of first P-type regions, a plurality of second P-type regions, and N-type regions. The first P-type regions and the second P-type regions lacking an ohmic contact are spaced apart with dimensions of the second P-type regions being minimized and the N-type regions being maximized for given dimensions of the first P-type region. Second ohmic contacts are located between the first P-type region and the Schottky metal layer.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: April 23, 2024
    Assignee: XIAMEN SANAN INTEGRATED CIRCUIT CO., LTD.
    Inventors: Yonghong Tao, Zhidong Lin, Zhigao Peng