Patents Examined by Monica D. Harrison
  • Patent number: 10930571
    Abstract: A method for detecting overlay misalignment of a semiconductor device uses a test structure that includes a sensor structure and a via-chain structure. The sensor structure is disposed in a first layer on a semiconductor substrate and includes a plurality of first conductive lines extending in a first direction. Each first conductive line is separated from an adjacent first conductive line in a second direction by a first space. The via-chain structure is in a second layer above the first layer and between the first layer and the second layer. The via-chain structure includes at least one second conductive line disposed in the second layer and at least one via electrically connected to each second conductive line and extending toward the first layer. The at least one via is disposed in the first space between the adjacent first conductive lines of the sensor structure.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 23, 2021
    Inventors: Ki-Don Lee, Zack Tran Mai
  • Patent number: 10916686
    Abstract: An optoelectronic component includes an optoelectronic semiconductor chip having a radiation-emitting face; and an optical element arranged over the radiation-emitting face, wherein the optical element includes a material in which light-scattering particles are embedded, and a concentration of the embedded light-scattering particles has a gradient forming an angle not equal to 90° with the radiation emission face.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: February 9, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Thomas Schwarz, Frank Singer, Alexander Linkov, Stefan Illek, Wolfgang Moench
  • Patent number: 10916726
    Abstract: There is provided a crack extension blocking structure used for a thin film encapsulation in a display panel and a production method thereof. the crack extension blocking structure has a first side wall, a top wall, a second side wall, and a bottom wall, which are sequentially connected, wherein the bottom wall is adjacent to a substrate of the display panel, wherein the second side wall is inclined to the first side wall along a direction from the top wall to the bottom wall, and an included angle between the first side wall and the bottom wall is less than or equal to 90 degrees. There is also provided a method of producing this crack extension blocking structure from a negative photoresist by a half-tone mask. There is also provided a display panel, a production method thereof, and a display apparatus.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 9, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Wei Wang, Peng Huang, Jingkai Ni
  • Patent number: 10903205
    Abstract: A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: January 26, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ting-Yao Lin, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
  • Patent number: 10903261
    Abstract: An infrared photo-detector and a method for manufacturing it are disclosed. The infrared photo-detector contains a collector region, a first absorber layer absorbing a first wavelength band of incident light, wherein the first absorber layer is disposed between the collector region and the incident light, a second absorber layer absorbing a second wavelength band of light, wherein the first absorber layer is disposed between the second absorber layer and the incident light, at least one first electrical contact coupled with the first absorber layer, at least one second electrical contact coupled with the second absorber layer and at least one third electrical contact coupled with the collector, wherein the at least one third electrical contact provides a current associated with absorbed light of the first wavelength band and absorbed light of the second wavelength band. The method disclosed teaches how to manufacture the infrared photo-detector.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 26, 2021
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Rajesh D. Rajavel
  • Patent number: 10903290
    Abstract: The present disclosure provides a display device. The display device including a substrate, a planarization layer formed on the substrate, a transparent electrode formed on the planarization layer, and a pixel defining layer formed on the transparent electrode. The pixel defining layer is configured to define a display area for each pixel and having an opening corresponding to the display area. The display device further includes a light emitting layer formed on the pixel defining layer, a metal electrode formed on the light emitting layer, and a hydrogen-atom blocking material layer formed on the metal electrode.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: January 26, 2021
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO.. LTD.
    Inventors: Xiang Wan, Wenbin Jia
  • Patent number: 10892226
    Abstract: A power semiconductor module may include a first plate, a second plate configured to include first and second device receiving portions thereinside, and coupled to one side of the first plate, first and second power semiconductor devices arranged in the first and second device receiving portions, first and second input bus bars coupled to an outside of the second plate, a third plate configured to include third and fourth device receiving portions thereinside, and coupled to the other side of the first plate, third and fourth power semiconductor devices arranged in the third and fourth device receiving portions, and third and fourth input bus bars coupled to an outside of the third plate.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: January 12, 2021
    Assignee: LSIS CO., LTD.
    Inventor: Teagsun Jung
  • Patent number: 10876220
    Abstract: A SiC epitaxial wafer includes: a substrate having an off angle of less than 4 degrees; and a SiC epitaxial growth layer disposed on the substrate having the off angle of less than 4 degrees, wherein an Si compound is used for a supply source of Si, and a C compound is used as a supply source of C, for the SiC epitaxial growth layer, wherein the uniformity of carrier density is less than 10%, and the defect density is less than 1 count/cm2; and a C/Si ratio of the Si compound and the C (carbon) compound is within a range of 0.7 to 0.95. There is provide a high-quality SiC epitaxial wafer excellent in film thickness uniformity and uniformity of carrier density, having the small number of surface defects, and capable of reducing costs, also in low-off angle SiC substrates on SiC epitaxial growth.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 29, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Hirokuni Asamizu
  • Patent number: 10879274
    Abstract: An object is to provide a semiconductor device using an oxide semiconductor having stable electric characteristics and high reliability. A transistor including the oxide semiconductor film in which a top surface portion of the oxide semiconductor film is provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film and functioning as a channel protective film is provided. In addition, the oxide semiconductor film used for an active layer of the transistor is an oxide semiconductor film highly purified to be electrically i-type (intrinsic) by heat treatment in which impurities such as hydrogen, moisture, a hydroxyl group, or a hydride are removed from the oxide semiconductor and oxygen which is a major constituent of the oxide semiconductor and is reduced concurrently with a step of removing impurities is supplied.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: December 29, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10872895
    Abstract: A method of manufacturing a semiconductor device includes forming a source/drain region in a substrate. An interlevel dielectric layer is formed on the substrate. A conducting plug is formed in the interlevel dielectric layer. The conducting plug is electrically coupled to the source/drain region. A crown oxide is formed on the interlevel dielectric layer. A deep trench is formed in the crown oxide to expose a top wall and a sidewall of the conducting plug. A spacer is formed on the sidewall of the conducting plug. A metal-insulator-metal film is formed in the deep trench.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Hsueh Yang, Chung-Chiang Min, Chang-Ming Wu, Shih-Chang Liu
  • Patent number: 10868172
    Abstract: A semiconductor device includes: a gate trench extending into a Si substrate; a body region in the Si substrate, the body region including a vertical channel region adjacent a sidewall of the gate trench; a source region in the Si substrate above the body region; a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and by a portion of the body region; an electrically conductive material in the contact trench; and a diffusion barrier structure interposed between a sidewall of the contact trench and the vertical channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and configured to increase carrier mobility within the vertical channel region. Corresponding methods of manufacture are also described.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Thomas Feil, Maximilian Roesch, Martin Poelzl, Robert Haase, Sylvain Leomant, Bernhard Goller, Andreas Meiser
  • Patent number: 10867793
    Abstract: A semiconductor package includes a substrate and a redistribution structure. The substrate has at least one contact. The redistribution structure is disposed on the substrate and electrically connected to the at least one contact, wherein the redistribution structure includes a plurality of redistribution layers. Each of the redistribution layers include a seed layer, a conductive material layer and a dielectric material layer. The conductive material layer is disposed on the seed layer. The dielectric material layer is surrounding the conductive material layer and the seed layer. At least one of the redistribution layers include an anti-reflective layer disposed in between the seed layer and the conductive material layer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Hung-Jui Kuo, Ming-Che Ho, Ming-Tan Lee, Tzung-Hui Lee
  • Patent number: 10861853
    Abstract: A semiconductor device includes a substrate having first and second regions, a first gate electrode layer on the first region, and including a first conductive layer, and a second gate electrode layer on the second region, and including the first conductive layer, a second conductive layer on the first conductive layer, and a barrier metal layer on the second conductive layer, wherein an upper surface of the first gate electrode layer is at a lower level than an upper surface of the second gate electrode layer.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se Ki Hong, Ju Youn Kim, Jin Wook Kim
  • Patent number: 10861901
    Abstract: A resistive random access memory including a stacked structure, at least one vertical electrode, a selector element, and a plurality of resistance changeable structures is provided. The stacked structure is formed by a plurality of horizontal electrodes and a plurality of first dielectric layers stacked alternately, wherein the stacked structure has at least one channel hole extending through the horizontal electrodes and the first dielectric layers. The vertical electrode is formed in the at least one channel hole. The selector element is formed in the channel hole between the vertical electrode and the stacked structure. The resistance changeable structures are disposed on the surface of each of the horizontal electrodes and are in contact with the selector element in the channel hole.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: December 8, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Zih-Song Wang
  • Patent number: 10861966
    Abstract: A semiconductor device includes: a gate trench extending into a Si substrate; a body region in the Si substrate adjacent the gate trench; a source region in the Si substrate above the body region; a diffusion barrier structure adjacent a sidewall of the gate trench, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; and a channel region formed in the Si capping layer and which vertically extends along the sidewall of the gate trench. Corresponding methods of manufacture are also described.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 8, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Robert Haase, Martin Poelzl, Maximilian Roesch, Sylvain Leomant, Bernhard Goller, Ravi Keshav Joshi
  • Patent number: 10851454
    Abstract: A method of forming conformal amorphous metal films is disclosed. A method of forming crystalline metal films with a predetermined orientation is also disclosed. An amorphous nucleation layer is formed on a substrate surface. An amorphous metal layer is formed from the nucleation layer by atomic substitution. A crystalline metal layer is deposited on the amorphous metal layer by atomic layer deposition.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: December 1, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Yong Wu, Srinivas Gandikota, Abhijit Basu Mallick
  • Patent number: 10854595
    Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wun-Jie Lin, Han-Jen Yang, Yu-Ti Su
  • Patent number: 10854461
    Abstract: Methods for depositing a metal film without the use of a barrier layer are disclosed. Some embodiments comprise forming an amorphous nucleation layer comprising one or more of silicon or boron and forming a metal layer on the nucleation layer.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 1, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Yihong Chen, Yong Wu, Chia Cheng Chin, Srinivas Gandikota, Kelvin Chan
  • Patent number: 10847660
    Abstract: A method of forming a semiconductor device includes providing a region of semiconductor material comprising a major surface. A termination trench is provided extending from a first portion of the major surface into the region of semiconductor material to a first depth and has a first width. A first active trench is provided extending from a second portion of the major surface into the region of semiconductor material to a second depth and has a second width less than the first width. A second active trench is provided extending from a third portion of the major surface into the region of semiconductor material to a third depth and has a third width less than the first width. A first conductive material is provided adjoining a fourth portion of the major surface, which is configured as a Schottky barrier. The selected trench depth difference alone or in combination with other features provides a semiconductor device having improved performance characteristics.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: November 24, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Michael Thomason
  • Patent number: 10840466
    Abstract: Disclosed herein is an electronic device including a first electrode, a second electrode, and a photoelectric conversion layer held between the first electrode and the second electrode. The first electrode is formed from a transparent conductive material having a work function ranging from 5.2 to 5.9 eV, preferably from 5.5 to 5.9 eV, more preferably 5.8 to 5.9 eV.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: November 17, 2020
    Assignee: SONY CORPORATION
    Inventor: Toshiki Moriwaki