Patents Examined by Monica D. Harrison
  • Patent number: 11322516
    Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Matthew J. King, David A. Daycock, Yoshiaki Fukuzumi, Albert Fayrushin, Richard J. Hill, Chandra S. Tiwari, Jun Fujiki
  • Patent number: 11316005
    Abstract: A display device includes a substrate including a bending area located between a first area and a second area. The substrate is bent in relation to a bending axis. A first wiring unit including a plurality of first wirings is arranged on the substrate to sequentially extend over the first area, the bending area, and the second area. First central axes included in each of the plurality of first wirings are spaced apart from each other by a first pitch in the bending area. A second wiring unit including a plurality of second wirings is arranged on the substrate to sequentially extend over the first area, the bending area, and the second area. Second central axes included in each of the plurality of second wirings are spaced apart from each other by a second pitch greater than the first pitch in the bending area.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yangwan Kim, Sunja Kwon, Byungsun Kim, Hyunae Park, Sujin Lee, Jaeyong Lee
  • Patent number: 11316052
    Abstract: A junction barrier schottky (JBS) diode is provided and includes: a bottom metal layer, a N+-type substrate layer and a N?-type epitaxial layer sequentially arranged in that order from bottom to top, P-type ion injection regions are disposed on an upper surface of the N?-type epitaxial layer, distances of the P-type ion injection regions are gradually increased along a direction from an edge to a center of the JBS diode; an isolation dielectric layer is arranged on a periphery of the upper surface of the N?-type epitaxial layer, an top metal layer is arranged on the upper surface of the N?-type epitaxial layer and an upper surface of the isolation dielectric layer and further is in contact with the P-type ion injection regions. The JBS diode can effectively inhibit an occurrence of local electromigration and improve a device reliability.
    Type: Grant
    Filed: May 9, 2020
    Date of Patent: April 26, 2022
    Assignee: XIDIAN UNIVERSITY
    Inventors: Qingwen Song, Xiaoyan Tang, Yuming Zhang, Hao Yuan, Chao Han
  • Patent number: 11316050
    Abstract: A BCE IGZO TFT device and a manufacturing method thereof include steps of providing a substrate, depositing a first metal layer on the substrate, wherein the first metal layer forms a gate and a first electrode layer by a patterning process, depositing a gate insulating layer on the substrate, the gate, and the first electrode layer, wherein the gate insulating layer is etched to remove a part of the gate insulating layer on a surface of the first electrode layer, depositing an active layer on the first electrode layer and the gate insulating layer, wherein the active layer and the first electrode layer are in direct contact, and depositing a second metal layer on the active layer, wherein the second metal layer forms a source, a drain, and a second electrode layer by a patterning process.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: April 26, 2022
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Wei Wu
  • Patent number: 11316025
    Abstract: An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first and a second face, opposite to one another along a first direction, which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal, which extends at the first face of the semiconductor body; a second conduction terminal, which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer, of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 26, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Patrick Fiorenza, Fabrizio Roccaforte, Mario Giuseppe Saggio
  • Patent number: 11308833
    Abstract: An information terminal capable of switching display and non-display of images by strain. The information terminal includes a display portion and a strain sensor. The display portion includes a liquid crystal element, a light-emitting element, and a first and a second transistors. The strain sensor includes a strain sensor element and a resistor. The first transistor has a function of controlling current flowing into the light-emitting element. The strain sensor element has a function as a variable resistor. A first terminal of the strain sensor element is electrically connected to a first terminal of the resistor. A gate of the first transistor is electrically connected to a first terminal of the strain sensor element via the second transistor.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: April 19, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yuki Okamoto
  • Patent number: 11309438
    Abstract: A semiconductor device having, in a plan view, a termination region surrounding an active region. The semiconductor device includes a semiconductor substrate containing silicon carbide, a first-conductivity-type region provided in the semiconductor substrate at its first main surface, a plurality of first second-conductivity-type regions selectively formed in the semiconductor substrate at its first main surface, a plurality of silicide films respectively in ohmic contact with the first second-conductivity-type regions, a first electrode that is in contact with the silicide films to form ohmic regions, with the first second-conductivity-type regions to form non-operating regions, and with the first-conductivity-type region to form Schottky regions, a second electrode provided at a second main surface of the semiconductor substrate, and a second second-conductivity-type region provided in the termination region.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: April 19, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Ohse, Takahito Kojima, Yuichi Hashizume, Takafumi Uchida
  • Patent number: 11309437
    Abstract: Provided are a vertical Schottky barrier diode using a two-dimensional layered semiconductor and a fabrication method thereof, the vertical Schottky barrier diode having excellent response characteristics in a high frequency region and capable of being directly fabricated from a material having a low melting point such as glass or plastic because its fabrication process is performed at a relatively low temperature. The vertical Schottky barrier diode includes: an ohmic contact layer formed of a metal; a two-dimensional layered semiconductor formed of two-dimensional transition metal dichalcogenides (TMDs) on one surface of the ohmic contact layer; a Schottky contact layer formed on one surface of the two-dimensional layered semiconductor; and a non-conductive layer formed on the other surface of the ohmic contact layer or one surface of the Schottky contact layer.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: April 19, 2022
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seongil Im, Sung Jin Yang
  • Patent number: 11309287
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 19, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11302790
    Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Leonard P. Guler, Biswajeet Guha, Mark Armstrong, William Hsu, Tahir Ghani, Swaminathan Sivakumar
  • Patent number: 11296107
    Abstract: Embodiments of a memory finger structure and architecture for a three-dimensional memory device and fabrication method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate, the alternating layer stack including a plurality of conductor/dielectric layer pairs. The memory device further includes a first column of vertical memory strings extending through the alternating layer stack, and a first plurality of bitlines displaced along a first direction and extending along a second direction. The first column of vertical memory strings is disposed at a first angle relative to the second direction. Each of the first plurality of bitlines is connected to an individual vertical memory string in the first column.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 5, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Jun Liu
  • Patent number: 11289402
    Abstract: A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Wuk Park, Sung Dong Cho, Eun Ji Kim, Hak Seung Lee, Dae Suk Lee, Dong Chan Lim, Sang Jun Park
  • Patent number: 11282963
    Abstract: Low temperature thin film transistors and micro light-emitting diode displays having low temperature thin film transistors are described. In an example, an integrated circuit structure includes a gate electrode on an insulator structure. A channel material layer is over the gate electrode and extends beyond a first side and a second side of the gate electrode. The channel material layer includes a crystalline Group III-P material. A first conductive contact is on a portion of the channel material layer extending beyond the first side of the gate electrode. A second conductive contact is on a portion of the channel material layer extending beyond the second side of the gate electrode.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventor: Khaled Ahmed
  • Patent number: 11281030
    Abstract: Novel and useful electronic and magnetic control of several quantum structures that provide various control functions. An electric field provides control and is created by a voltage applied to a control terminal. Alternatively, an inductor or resonator provides control. An electric field functions as the main control and an auxiliary magnetic field provides additional control on the control gate. The magnetic field is used to control different aspects of the quantum structure. The magnetic field impacts the spin of the electron by tending to align to the magnetic field. The Bloch sphere is a geometrical representation of the state of a two-level quantum system and defined by a vector in x, y, z spherical coordinates.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 22, 2022
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11276737
    Abstract: A method of forming a pattern part includes forming a first film on a target object, the first film having a first cure shrinkage ratio, forming a second film on the first film, the second film having a second cure shrinkage ratio greater than the first cure shrinkage ratio, and patterning the first film and the second film to form a pattern.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: March 15, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seungcheol Ko, Junho Sim, Seyoon Oh
  • Patent number: 11270977
    Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 8, 2022
    Assignee: XILINX, INC.
    Inventors: Praful Jain, Steven P. Young, Martin L. Voogel, Brian C. Gaide
  • Patent number: 11264504
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scheme of active and dummy fin structures and methods of manufacture. The structure includes: an active fin structure; at least one dummy fin structure running along at least one side of the active fin structure along its length; a fin cut separating the at least one dummy fin structure along its longitudinal axes; and a gate structure extending over the active fin structure and the fin cut.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: March 1, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Yanping Shen, Haiting Wang, Hong Yu
  • Patent number: 11257690
    Abstract: A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wensen Hung
  • Patent number: 11257807
    Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: February 22, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ting-Yao Lin, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
  • Patent number: 11257959
    Abstract: A semiconductor device having a high on-state current is provided. The semiconductor device includes a first oxide; a first conductor and a second conductor provided over the first oxide to be separated from each other; and a second oxide provided over the first oxide and between the first conductor and the second conductor. Each of the first oxide and the second oxide has crystallinity, the first oxide includes a region where a c-axis is aligned substantially perpendicularly to a top surface of the first oxide, and the second oxide includes a region where the c-axis is aligned substantially perpendicularly to the top surface of the first oxide, a region where the c-axis is aligned substantially perpendicularly to a side surface of the first conductor, and a region where the c-axis is aligned substantially perpendicularly to a side surface of the second conductor.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: February 22, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tsutomu Murakawa, Hiroki Komagata, Katsuaki Tochibayashi, Kentaro Sugaya