Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.

Abstract: Methods for depositing a silicon-germanium film on a substrate are described. The method comprises exposing a substrate to a silicon precursor and a germanium precursor to form a conformal silicon-germanium film. The substrate comprises at least one film stack and at least one feature, the film stack comprising alternating layers of silicon and silicon-germanium. The silicon-germanium film has a conformality greater than 50%.

Abstract: Disclosed is a method for suppressing material warpage by increasing a gas density. The method comprises the following steps: a. placing a plurality of semiconductor elements in a processing chamber; b. increasing a temperature in the processing chamber to a first predetermined temperature and importing a gas, to increase pressure to predetermined pressure and apply the processing chamber in a high-temperature and high-pressure working environment; and performing an isothermal-isobaric process at the first predetermined temperature and the predetermined pressure, to improve temperature uniformity by the high pressure gas; and c. decreasing the temperature in the processing chamber from the first predetermined temperature to a second predetermined temperature and continuing to import the gas into the processing chamber, to maintain the processing chamber at the predetermined pressure; and performing a cooling and isobaric process on each semiconductor element, to suppress warpage of each semiconductor element.

Abstract: An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a gate structure which extends along a first direction, and a plurality of supporting patterns which are separated from each other and arranged along a second direction which is perpendicular to the first direction.

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.

Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.

Abstract: A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor channel layer, a gate structure, complex regions, a source terminal and a drain terminal. The gate structure is disposed on the semiconductor channel layer. The source terminal and the drain terminal are disposed on the semiconductor channel layer. The complex regions ae respectively disposed between the source terminal and the semiconductor channel layer and between the drain terminal and the semiconductor channel layer.

Abstract: A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench.

Abstract: A thin film forming method includes: a first operation of supplying a source gas at a first flow rate into a reactor; a second operation of purging the source gas in the reactor to an exhaust unit; a third operation of supplying a reactive gas at a second flow rate into the reactor; a fourth operation of supplying plasma into the reactor; and a fifth operation of purging the reactive gas in the reactor to the exhaust unit, wherein, during the second to fifth operations, the source gas is bypassed to the exhaust unit, and a flow rate of the source gas bypassed to the exhaust unit is less than the first flow rate. According to the thin film forming method, the consumption of the source gas and the reactive gas may be reduced, and the generation of reaction by-products in the exhaust unit may be minimized.

Abstract: Disclosed is a semiconductor module including a substrate, a first semiconductor layer positioned on the substrate, an insulator positioned in a partial region on the first semiconductor layer, a second semiconductor layer positioned on the insulator, a first semiconductor device formed on the first semiconductor layer, and a second semiconductor device formed on the second semiconductor layer, wherein one of the first semiconductor layer and the second semiconductor layer includes gallium oxide (Ga2O3) and the other includes silicon (Si).

Abstract: A bottom portion of a Ta pillar serving as a contact portion is connected to an N+ layer and a P+ layer, and a gate HfO2 layer is connected to side surfaces of Si pillars and a Ta pillar serving as a contact portion and an upper surface of a SiO2 layer between the Si pillars and the Ta pillar serving as the contact portion. Gate TiN layers are provided on a side surface of the gate HfO2 layer surrounding the Si pillars. Midpoints of the Si pillars and the Ta pillar serving as the contact portion are on one first line in plan view.

Abstract: A method for forming a semiconductor device is provided. The method for forming a semiconductor device is provided. The method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer; performing a directional ion bombardment process to the photoresist layer, such that a carbon atomic concentration in the photoresist layer is increased; and etching the target layer using the photoresist layer as an etch mask.

Abstract: In a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate dielectric layer and contacting the gate dielectric layer; and a pair of source/drain regions on opposing sides of the gate dielectric layer.

Abstract: A substrate structure of the memory, and a method for preparing the substrate structure of the memory are provided. The method includes: providing a substrate; forming a first mask layer on the substrate, the first mask layer including a plurality of strip patterns extending in a direction and spaced apart from each other; forming a first dielectric layer covering the first mask layer; forming a plurality of sacrificial portions spaced apart from each other in the first dielectric layer and covering a portion of the plurality of strip patterns; filling gaps between the sacrificial portions with a second dielectric material; forming a second mask layer by removing the sacrificial portions while retaining the second dielectric material in the gaps; and performing layer-by-layer etching into the substrate to form a plurality of active areas arranged in an array.

Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.

Abstract: A semiconductor structure and a forming method thereof are provided. The method of forming the semiconductor structure includes: providing a wafer having a front surface and a back surface opposite to the front surface; patterning the back surface of the wafer to form a groove extending from the back surface towards the front surface; forming a dielectric layer at a bottom and a side wall of the groove; and forming, on the dielectric layer, a conductive layer filling the groove.