Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, and third semiconductor regions, an insulating part, a conductive part, and a gate electrode. The first semiconductor region is provided on the first electrode and is electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating part is provided on the first electrode. The conductive part is provided in the insulating part and is arranged with the first semiconductor region. The gate electrode is provided in the insulating part. The gate electrode is positioned above the conductive part and is arranged with the second semiconductor region. The second electrode is provided on the third semiconductor region and the insulating part, and is electrically connected to the third semiconductor region.

Abstract: Methods of forming silicon nitride thin films on a substrate in a reaction space under high pressure are provided. The methods can include a plurality of plasma enhanced atomic layer deposition (PEALD) cycles, where at least one PEALD deposition cycle comprises contacting the substrate with a nitrogen plasma at a process pressure of 20 Torr to 500 Torr within the reaction space. In some embodiments the silicon precursor is a silyl halide, such as H2SiI2. In some embodiments the processes allow for the deposition of silicon nitride films having improved properties on three dimensional structures. For example, such silicon nitride films can have a ratio of wet etch rates on the top surfaces to the sidewall of about 1:1 in dilute HF.

Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.

Abstract: The method includes providing a to-be-etched layer including an first region and a second region adjoining the first region, forming a first mask layer on the to-be-etched layer, forming a patterned core layer on the first mask layer of the first region, forming a sidewall spacer on the core layer and the first mask layer, forming a first sacrificial layer on the sidewall spacer on the surface of the first mask layer of the second region, forming a second sacrificial layer on the sidewall spacer, removing the first sacrificial layer, the sidewall spacer on the surface of the first mask layer of the second region, and the sidewall spacer on a top of the core layer, removing the core layer, etching the first mask layer of the first region to form a first trench, and etching the first mask layer of the second region to form a second trench.

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: A semiconductor device includes: a stacked structure comprising a plurality of dielectric layers and a plurality of conductive layers, wherein the dielectric layers are alternately stacked with the conductive layers; a groove formed for each conductive layer by recessing the conductive layer to the inside of the stacked structure; and an isolation structure formed through the stacked structure so as to isolate the stacked structure into a first block and a second block. The isolation structure comprises a first isolation structure and a second isolation structure adjacent to the first isolation structure with a gap provided between the first and second isolation structures, and one end of the first isolation structure and the other end of the second isolation structure, which face each other, have a vortex shape when viewed from above.

Abstract: According to an embodiment of a semiconductor device, the device includes: a plurality of device cells formed in a semiconductor substrate, each device cell including a transistor structure and a Schottky diode structure; and a superjunction structure that includes alternating regions of a first conductivity type and of a second conductivity type formed in the semiconductor substrate. For each transistor structure, a channel region of the transistor structure and a Schottky metal region of an adjacent one of the Schottky diode structures are interconnected by semiconductor material of the first conductivity type without interruption by any of the regions of the second conductivity type of the superjunction structure, the semiconductor material of the first conductivity type including one or more of the regions of the first conductivity type of the superjunction structure.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor channel layer, a gate structure, complex regions, a source terminal and a drain terminal. The gate structure is disposed on the semiconductor channel layer. The source terminal and the drain terminal are disposed on the semiconductor channel layer. The complex regions are respectively disposed between the source terminal and the semiconductor channel layer and between the drain terminal and the semiconductor channel layer.

Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first gate-all-around (GAA) transistor that includes a first plurality of channel members, and a second GAA transistor that includes a second plurality of channel members. The first plurality of channel members has a first pitch (P1) and the second plurality of channel members has a second pitch (P2) smaller than the first pitch (P1).

Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.

Abstract: A spin on carbon composition, comprises: a carbon backbone polymer; a first crosslinker; and a second crosslinker. The first crosslinker reacts with the carbon backbone polymer to partially crosslink the carbon backbone polymer at a first temperature, and the second crosslinker reacts with the carbon backbone polymer to further crosslink the carbon backbone polymer at a second temperature higher than the first temperature. The first crosslinker is a monomer, oligomer, or polymer. The second crosslinker is a monomer, oligomer, or polymer. The first and second crosslinkers are different from each other. When either of the first crosslinker or the second crosslinker is a polymer, the polymer is a different polymer than the carbon backbone polymer.

Abstract: Embodiments of a memory finger structure and architecture for a three-dimensional memory device and fabrication method thereof are disclosed. The method includes forming an alternating layer stack, forming a plurality of slit structures, forming a plurality of conductor/dielectric layer pairs, forming a first column of vertical memory strings, forming a second column of vertical memory strings, and forming a plurality of bitlines. The plurality of slit structures each extend vertically through the alternating layer stack and laterally along a wordline direction to divide the alternating layer stack into at least one memory finger. The vertical memory strings in the first column are displaced relative to each other along the wordline direction. The vertical memory strings in the second column are displaced relative to each other along the wordline direction. Each bitline is connected to an individual vertical memory string in the first and second columns.

Abstract: An electronic device can include a gate structure. In an embodiment, the gate structure can include a gate electrode including a doped semiconductor material, a metal-containing member, a pair of conductive sidewall spacers. The first metal-containing member can overlie the gate electrode. The conductive sidewall spacers can overlie the gate electrode and along opposite sides of the first metal-containing member. In another embodiment, the gate structure can include a gate electrode, a first metal-containing member overlying the gate electrode, and a second metal-containing member overlying the first metal-containing member. The first metal-containing member can have a length that is greater than the length of the second metal-containing member and substantially the same length as the gate electrode.

Abstract: An electronic device includes a solid body of SiC having a surface and having a first conductivity type. A first implanted region and a second implanted region have a second conductivity type and extend into the solid body in a direction starting from the surface and delimit between them a surface portion of the solid body. A Schottky contact is on the surface and in direct contact with the surface portion. Ohmic contacts are on the surface and in direct contact with the first and second implanted regions. The solid body includes an epitaxial layer including the surface portion and a bulk portion. The surface portion houses a plurality of doped sub-regions which extend in succession one after another in the direction, are of the first conductivity type, and have a respective conductivity level higher than that of the bulk portion.

Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

Abstract: Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure manufacturing method includes: providing a base substrate and an array region, the array region being composed of strip structures arranged in parallel, the base substrate being made of a same material as the array region, and a thickness of the base substrate being greater than a thickness of the array region; etching the strip structure to form discrete first strip structures; base substrate providing a second mask layer, an opening pattern of the second mask layer exposing the to-be-etched region and the side plane, and a right angle being formed between an orthographic projection of the side plane and the opening pattern; form a first active region, the first active region having a mapping right angle corresponding to the right angle.

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device may include a first device provided on a first region of a substrate; and a second device provided on a second region of the substrate, wherein the first device may include a first domain layer including a ferroelectric domain and a first gate electrode on the first domain layer, and the second device may include a second domain layer including a ferroelectric domain and a second gate electrode on the second domain layer. The first domain layer and the second domain layer may have different characteristics from each other at a polarization change according to an electric field. At the polarization change according to the electric field, the first domain layer may have substantially a non-hysteretic behavior characteristic and the second domain layer may have a hysteretic behavior characteristic.

Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.