Abstract: An integrated circuit assembly including a substrate having a surface including at least one area including contact points operable for connection with an integrated circuit die; and at least one ring surrounding the at least one area, the at least one ring including an electrically conductive material. A method of forming an integrated circuit assembly including forming a plurality of electrically conductive rings around a periphery of a die area of a substrate selected for attachment of at least one integrated circuit die, wherein the plurality of rings are formed one inside the other; and forming a plurality of contact points in the die area.

Abstract: A hybrid wafer bonding method includes providing a first semiconductor structure and providing a second semiconductor structure. The first semiconductor structure includes a first substrate, a first dielectric, and a first via structure. The first via structure includes a first contact via and first metal impurities doped in the first contact via. The second semiconductor structure includes a second substrate, a second dielectric layer, and a second via structure. The second via structure includes a second contact via and second metal impurities doped in the second contact via. The method further includes bonding the first semiconductor structure with the second semiconductor and forming a self-barrier layer by an alloying process. The self-barrier layer is formed by a multi-component oxide corresponding to the first and second metal impurities.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method includes: forming a silicide layer, forming a vertical Si channel layer, wherein the vertical Si channel layer is on an upper surface of the silicide layer, the vertical Si channel layer has a first silicon phase; performing a first annealing step so as to move the silicide layer upward and change a solid phase of the vertical Si channel layer from the first silicon phase to a second silicon phase at an interface of the silicide layer and the vertical Si channel layer, wherein the second silicon phase has a conductivity higher than a conductivity of the first silicon phase.

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

Abstract: A semiconductor device with enhanced semiconductor characteristics that is useful for power devices. A semiconductor device, including: an n-type semiconductor layer; an electrode; two or more p-type semiconductors provided between the n-type semiconductor layer and the electrode, the n-type semiconductor layer containing a corundum-structured crystallin oxide semiconductor as a major component, a number of the two or more p-type semiconductor that is equal to or more than three, and the two or more p-type semiconductors that are embedded in the n-type semiconductor layer.

Abstract: A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.

Abstract: Semiconductor devices and methods of forming the same are disclosed. The semiconductor devices may include a substrate including a first region and a second region, which are spaced apart from each other with a device isolation layer interposed therebetween, a first gate electrode and a second gate electrode on the first and second regions, respectively, an insulating separation pattern separating the first gate electrode and the second gate electrode from each other and extending in a second direction that traverses the first direction, a connection structure electrically connecting the first gate electrode to the second gate electrode, and a first signal line electrically connected to the connection structure. The first and second gate electrodes are extended in a first direction and are aligned to each other in the first direction. The first signal line may extend in the second direction and may vertically overlap the insulating separation pattern.

Abstract: An organic light-emitting display device and method of manufacturing the same are provided. An organic light-emitting display device includes: a substrate, an organic light-emitting device on the substrate, an encapsulation layer on the substrate and the organic light-emitting device, the encapsulation layer covering the organic light-emitting device, the encapsulation layer including an encapsulation hole, a black matrix covering the encapsulation layer, the black matrix including a black matrix hole over the encapsulation hole, and a color filter in the encapsulation hole and the black matrix hole.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate structure on the first region, a second gate structure on the second region, and a third gate structure on the third region; forming an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure; removing the first gate structure, the second gate structure, and the third gate structure to form a first recess, a second recess, and a third recess; forming a first interfacial layer in the first recess, the second recess, and the third recess; removing the first interfacial layer in the second recess; and forming a second interfacial layer in the second recess.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first semiconductor substrate having a photodetector and a floating diffusion node. A transfer gate is disposed over the first semiconductor substrate, where the transfer gate is at least partially disposed between opposite sides of the photodetector. A second semiconductor substrate is vertically spaced from the first semiconductor substrate, where the second semiconductor substrate comprises a first surface and a second surface opposite the first surface. A readout transistor is disposed on the second semiconductor substrate, where the second surface is disposed between the transfer gate and a gate of the readout transistor. A first conductive contact is electrically coupled to the transfer gate and extending vertically from the transfer gate through both the first surface and the second surface.

Abstract: A semiconductor device, including a first metal strip extending in a first direction on a first plane; a second metal strip extending in the first direction on a second plane over the first metal strip; a third metal strip immediate adjacent to the second metal strip and extending in the first direction on the second plane; and a fourth metal strip immediate adjacent to the third metal strip and extending in the first direction on the second plane; wherein the first metal strip and the second metal strip are directed to a first voltage source; wherein a distance between the second metal strip and the third metal strip is greater than a distance between the third metal strip and the fourth metal strip.

Abstract: An economical, efficient, and effective formation of a high resolution pattern of conductive material on a variety of films by polymer casting. This allows, for example, quite small-scale patterns with sufficient resolution for such things as effective microelectronics without complex systems or steps and with substantial control over the characteristics of the film. A final end product that includes that high resolution functional pattern on any of a variety of substrates, including flexible, stretchable, porous, biodegradable, and/or biocompatible. This allows, for example, highly beneficial options in design of high resolution conductive patterns for a wide variety of applications.

Abstract: A semiconductor package may include a semiconductor device coupled to a package substrate. The semiconductor package may also include an integrated heat spreader coupled to the package substrate. The semiconductor package may further include a package connector mounted on the integrated heat spreader. According to various examples, a semiconductor system is also described. The semiconductor system may include a first semiconductor package. The first semiconductor package may include a first package connector, and a first integrated heat spreader. The first package connector may be mounted on the first integrated heat spreader. The semiconductor system may also include a second semiconductor package. The second semiconductor package may include a second package connector, and a second integrated heat spreader. The second package connector may be mounted on the second integrated heat spreader. The first package connector may be electrically connected to the second package connector.

Abstract: Embodiments of staircase structures of a three-dimensional memory device and fabrication method thereof are disclosed. The semiconductor structure includes a first and a second film stacks, wherein the first film stack is disposed over the second film stack and has M1 number of layers. The second film stack has M2 number of layers. M1 and M2 are whole numbers. The semiconductor structure also includes a first and a second staircase structures, wherein the first staircase structure is formed in the first film stack and the second staircase structure is formed in the second film stack. The first and second staircase structures are next to each other with an offset.

Abstract: A method of forming a semiconductor device includes the following operations. A substrate is provided with a device and an insulating layer disposed over the device. A silicon-containing heterocyclic compound precursor and a first oxygen-containing compound precursor are introduced to the substrate, so as to form a zeroth dielectric layer on the insulating layer. A zeroth metal layer is formed in the zeroth dielectric layer. A silicon-containing linear compound precursor and a second oxygen-containing compound precursor are introduced to the substrate to form a first dielectric layer on the zeroth dielectric layer. A first metal layer is formed in the first dielectric layer.

Abstract: A trench MOS Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer stacked on the first semiconductor layer, includes a Ga2O3-based single crystal, and includes a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench electrode that is buried in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes an insulating dry-etching-damaged layer with a thickness of not more than 0.8 ?m in a region including the inner surface of the trench.

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first silicon-germanium film which is conformally formed inside a surface of the substrate of the first region and defines a first gate trench, a first gate insulating film which extends on the first silicon-germanium film along a profile of the first gate trench and is in physical contact with the first silicon-germanium film, a first metallic gate electrode on the first gate insulating film, a source/drain region formed inside the substrate on both sides of the first metallic gate electrode, a second gate insulating film in the second region and a second metallic gate electrode on the second gate insulating film.

Abstract: Present disclosure provides a transistor structure, including a substrate, a first gate over the substrate, a second gate over the substrate and laterally in contact with the first gate, a first conductive region of a first conductivity type in the substrate, self-aligning to a side of the first gate, and a second conductive region of the first conductivity type in the substrate, self-aligning to a side of the second gate. A method for manufacturing the transistor structure is also disclosed.

Abstract: Embodiments of the present invention are directed to heat transfer arrays, cold plates including heat transfer arrays along with inlets and outlets, and thermal management systems including cold-plates, pumps and heat exchangers. These devices and systems may be used to provide cooling of semiconductor devices and particularly such devices that produce high heat concentrations. The heat transfer arrays may include microjets, microchannels, fins, and even integrated microjets and fins.