Abstract: The present disclosure relates to a process of manufacturing a photomultiplier microcell. The process comprises providing an insulating layer over an active region; and implanting a dopant through the insulating layer to form a photosensitive diode in the active region. The insulating layer once formed is retained over the active region throughout the manufacturing process.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: A method of conducting an in situ reliability test on a cross-section of a device with layered structure at micron-scale and at least two electrodes. The method includes steps of locating an electron transparent cross-sectional portion of the device in a holder and transmitting a direct current bias voltage to the cross-sectional portion of the device through at least two electrodes of the device, and observing and quantifying the microstructural changes of the device cross-section on the holder. A system for conducting an in situ reliability test on a device with a layered structure at a micron-scale and at least two electrodes is also provided.

Abstract: The invention is a process for producing an electromechanical device including a movable portion that is able to deform with respect to a fixed portion. The process implements steps based on fabrication microtechnologies, applied to a substrate including an upper layer, an intermediate layer and a lower layer. These steps are: a) forming first apertures in the upper layer; b) forming an empty cavity in the intermediate layer, which step is referred to as a pre-release step because a central portion of the upper layer lying between the first apertures is pre-released; c) applying what is called a blocking layer to the upper layer, this layer covering the first apertures, the blocking layer and the central portion together forming a suspended microstructure above the empty cavity; d) producing a boundary trench in the suspended microstructure, so as to form, in this microstructure, a movable portion and a fixed portion, the movable portion forming a movable member of the electromechanical device.

Abstract: A Magnetoresistive Tunnel Junction (MTJ) includes a magnetic reference layer disposed between a first electrode and a resistive layer. The junction also includes a magnetic free layer disposed between the resistive layer and a second electrode. The surface area of the free layer is less than the surface area of the reference layer.

Abstract: A method for assembling a first substrate and a second substrate via metal adhesion layers, the method including: depositing, on a surface of each of the first and second substrates, a metal layer with a thickness controlled to limit surface roughness of each of the deposited metal layers to below a roughness threshold; exposing the metal layers deposited on the surface of the first and second substrates to air; directly adhering the first and second substrates by placing the deposited metal adhesion layers in contact, the surface roughness of the contacted layers being that obtained at an end of the depositing. The adhesion can be carried out in the air, at atmospheric pressure and at room temperature, without applying pressure to the assembly of the first and second substrates resulting from directly contacting the deposited metal adhesion layers.

Abstract: In one approach, a method of fabricating radiation detection devices includes: forming a structural layer overlying a frontside of a substrate; forming a metallic layer overlying the structural layer; releasing each of a plurality of devices on the substrate by etching a backside of the substrate, wherein each device comprises a plate and legs attached to the plate, the legs comprising at least a portion of the metallic layer; and sealing each of the plurality of devices, the sealing comprising: attaching a transparent cavity cap to the frontside of the substrate; and attaching a radiation-transparent substrate to the backside of the substrate.

Abstract: Embodiments of the disclosure generally relate to a method of improving quality of a barrier layer suitable for forming high aspect ratio through substrate vias. In one example, a method for depositing a barrier layer includes depositing a barrier layer in a hole formed in a substrate, exposing the deposited barrier layer to a processing gas at a pressure greater than about 2 bars, and, maintaining a temperature of the substrate between about 150 degrees and about 700 degrees Celsius while in the presence of the processing gas.

Abstract: An electrical connection structure providing better optical properties in a display includes an electrical connection unit, an interference layer, and an electrically insulating cover. The interference layer is positioned on a side of the electrical connection unit. The electrically insulating cover is positioned on the other side of the electrical connection unit and formed to cover the electrical connection unit. The electrical connection unit includes a metal layer to reflect light. The interference layer reflects light emitted from the electrically insulating cover towards a first side of the interference layer. A degree of reflectance of the first side of the interference layer is equal to the reflectance of the metal layer.

Abstract: An embodiment of a transistor has a semiconductor fin, a dielectric over the semiconductor fin, a control gate over the dielectric, and source/drains in the semiconductor fin and having upper surfaces below an uppermost surface of the semiconductor fin. Another embodiment of a transistor has first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.

Abstract: The present invention is directed to a magnetic tunnel junction (MTJ) memory element including a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; a magnetic fixed layer exchange coupled to the magnetic reference layer structure through an anti-ferromagnetic coupling layer; a magnesium oxide layer formed adjacent to the magnetic fixed layer; and a metal layer comprising nickel and chromium formed adjacent to the magnesium oxide layer. The magnetic reference layer structure includes a first and a second magnetic reference layers with a first perpendicular enhancement layer (PEL) interposed therebetween. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof. The magnetic fixed layer has a second invariable magnetization direction opposite to the first invariable magnetization direction.

Abstract: Methods of singulating semiconductor die. Specific implementations may include: providing a semiconductor wafer including a plurality of die located on a first side of the semiconductor wafer where the plurality of die include a desired thickness. The method may include etching a plurality of trenches into the semiconductor wafer from the first side of the semiconductor wafer where the plurality of trenches is located adjacent to a perimeter of the plurality of die. A depth of the plurality of trenches may be greater than the desired thickness of the plurality of die. The method may also include mounting the first side of the semiconductor wafer to a tape, thinning a second side of the semiconductor wafer, exposing the plurality of trenches while thinning the second side, and singulating the plurality of die through exposing the plurality of trenches.

Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.

Abstract: A packaging substrate is provided, which includes: a substrate body having a first region with a plurality of conductive pads and a second region adjacent to the first region, and a material layer formed on the second region to prevent the substrate body from warping. An electronic package having the packaging substrate is also provided.

Abstract: There is provided a technique for facilitating a patterning process by the DSA appropriately and efficiently. According to the technique described herein, there is provided a method of manufacturing a semiconductor device, including (a) accommodating in a process chamber a substrate having a guide pattern thereon; (b) supplying a plasma of a first process gas into the process chamber to subject the substrate to first one of a first process for hydrophilizing the substrate and a second process for hydrophobilizing the substrate; and (c) supplying a plasma of a second process gas into the process chamber to subject the substrate to second one of the first process and the second process other than the first one of the first process and the second process.

Abstract: A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of dummy contact plugs each electrically connected between two adjacent dummy wirings of the plurality of dummy wiring of the plurality of dummy wirings. No dummy wiring of the plurality of dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate.

Abstract: A method for manufacturing an array substrate comprises forming a pattern including an active layer, a gate insulating layer and a gate on a base substrate, and forming a pattern including an interlayer dielectric layer, a source, a drain and a pixel electrode through a single patterning process on the base substrate formed with the pattern of the active layer, the gate insulating layer and the gate. An array substrate and a display device are further provided.

Abstract: An LED die containing a gallium semiconductor layer is placed on a target substrate using a pick-up tool (PUT) attached to the LED die using metallic gallium. As a result of a laser lift-of (LLO) process to separate the gallium semiconductor layer from a substrate layer on which the gallium semiconductor layer is formed, a layer of gallium metal is formed on a surface of the LED die. The gallium layer is melted to form liquid gallium. A head of the PUT is contacted with the liquid gallium, whereupon the LED die is cooled such that the liquid gallium solidifies, attaching the LED die to the PUT. The PUT picks up and places the LED die at a desired location on a target substrate. The LED die can be heated to melt the gallium layer, allowing the PUT to be detached.

Abstract: A processing method of a silicon nitride film can modify a silicon nitride film such that the silicon nitride film has a required characteristic even if it is formed at a low temperature by CVD. The processing method of the silicon nitride film formed on a substrate by plasma CVD includes modifying a surface portion of the silicon nitride film by irradiating microwave hydrogen plasma to the silicon nitride film to remove hydrogens in the surface portion of the silicon nitride film with atomic hydrogens contained in the microwave hydrogen plasma.

Abstract: Disclosed are a method and a system for processing wafers in fabricating a semiconductor device where disposing chemicals and wafer heating are needed for chemical reaction. A wafer is placed above a wafer heater such that a second surface faces the wafer heater, and heated from the second surface. A chemical layer is formed on an opposing first surface. The wafer heater is sized and configured to be capable of heating the entire second surface, and adapted to produce a locally differential temperature profile if needed. During heating, an actual temperature profile on the wafer may be monitored and transmitted to a computing system, which may generate a target temperature profile and control the wafer heater to adjust local temperatures on the wafer according to the target temperature profile. A supplemental heater for heating the chemicals may be used for finer control of the wafer temperature.