Abstract: Semiconductor devices are provided which comprise III-V FINFET devices that are formed with different semiconductor fin widths to obtain different threshold voltages, as well as methods for fabricating such III-V FINFET devices. For example, a semiconductor device comprises first and second semiconductor fins, which are formed of a III-V compound semiconductor material, and which have a first width W1 and a second width W2, respectively, wherein W1 is less than W2. First and second gate structures of first and second FINFET devices are formed over a portion of the first and second semiconductor fins, respectively. The first FINFET device comprises a first threshold voltage and the second FINFET device comprises a second threshold voltage. The first threshold voltage is greater than the second threshold voltage as a result of the first width W1 being less than the second width W2.

Abstract: A liquid crystal display according to an exemplary embodiment of the present inventive concept includes: a first insulating substrate; a thin film transistor disposed on the first insulating substrate; a light blocking member disposed on the thin film transistor; and a spacer disposed on the light blocking member, wherein the spacer includes a main column spacer and a sub column spacer, and the sub column spacer is disposed between the main column spacer and has a stripe shape which extends in parallel to a gate line of the thin film transistor.

Abstract: The invention relates to a structure for radiofrequency applications comprising: a monocrystalline substrate, a polycrystalline silicon layer directly on the monocrystalline substrate, and an active layer on the polycrystalline silicon layer intended to receive radiofrequency components. At least a first portion of the polycrystalline silicon layer extending from an interface of the polycrystalline silicon layer with the monocrystalline substrate layer includes carbon and/or nitrogen atoms located at the grain boundaries of the polycrystalline silicon layer at a concentration of between 2% and 20%. A process for manufacturing such a structure includes, during deposition of at least a first portion of such a polycrystalline silicon layer located at the interface with the monocrystalline substrate, depositing carbon and/or atoms in the at least a first portion.

Abstract: A method of manufacturing an organic light-emitting display apparatus includes forming an anode on a substrate, forming a lift-off layer on the substrate including the anode, the lift-off layer including a fluoropolymer, forming a polymer layer on the lift-off layer, forming a pattern on a first portion of the polymer layer overlapping the anode using a roll-to-roll stamp process, etching a first portion of the lift-off layer corresponding to the pattern using a first solvent including fluorine, the first portion of the lift-off layer being disposed on the anode, forming an organic functional layer including a light-emitting layer on the anode and a second portion of the polymer layer not formed with the pattern, removing the lift-off layer using a second solvent including fluorine, and forming a cathode on the organic functional layer.

Abstract: A controllable semiconductor component is produced by providing a semiconductor body with a top side and a bottom side, and forming a first trench protruding from the top side into the semiconductor body and a second trench protruding from the top side into the semiconductor body. In a common process, an oxide layer is formed in the first trench and in the second trench such that the oxide layer fills the first trench and electrically insulates a surface of the second trench. The oxide layer is removed from the first trench completely or at least partly such that the semiconductor body has an exposed first surface area arranged in the first trench. An electrically conductive material is filled into the second trench, and the semiconductor body and the oxide layer are partially removed such that the electrically conductive material has an exposed second surface area at the bottom side.

Abstract: An apparatus for depositing an organic material includes: a main chamber; a first substrate loading section in which a first substrate is loaded in the first radial direction and seated; a second substrate loading section in which a second substrate is loaded in the second radial direction and seated; a scanner including a linear organic material deposition source, a source moving means to which the organic material deposition source is coupled to linearly move the organic material deposition source so that the organic material particles are injected onto the surface of the first substrate or the second substrate, and a rotating means for rotating the source moving means; and a scanner moving means for moving the scanner back and forth so that the scanner is positioned in the first deposition region or the second deposition region.

Abstract: The present invention relates generally to semiconductor structures and methods of manufacturing and, more particularly, to improving heat dissipation of devices, such as active devices like inductors, by filling portions of the semiconductor structure with thermally conductive and electrical isolating material that may serve as a heat sink to a base substrate. In an embodiment, an inductor may be formed above a cavity region in which the thermally conductive and electrical isolating material has been formed. Heat may then be dissipated from the inductor to the cavity, and eventually to the base substrate, through trenches filled with the thermally conductive and electrical isolating material.

Abstract: In a photo alignment process according to a manufacturing method of a liquid crystal display device including a display panel with a liquid crystal layer interposed between substrates, in order to even the exposure amount of ultraviolet light in an area of a substrate passing through the lower central portion of a bar-like UV lamp arranged in a prolonged way in a direction crossing the proceeding direction of the substrate and in an area of the substrate passing through the end portions thereof, the ultraviolet light is irradiated through an aperture having a larger opening width in the end portions than in the center portion.

Abstract: Disclosed herein are methods of fabricating a source side select (SGS) transistor in 3D memory. The threshold voltage of the SGS transistor accurately meets a target threshold voltage. The SGS transistor has a semiconductor body that resides in a memory hole formed in a stack of alternating layers of two materials. During fabrication, a sacrificial layer may be removed to create recesses between dielectric layers in a stack. The sacrificial layer may be removed by introducing an etchant into slits formed in the stack. Thus, the recess may expose sidewalls of the body of the SGS transistor. An impurity may be introduced into this recess, by way of a slit, in order to dope the source side select transistor. This allows for precise control over the doping profile, which in turn provides for precise control over the threshold voltage of the SGS transistor.

Abstract: A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers. The method further includes forming openings in the first imaging layer to expose a first set of areas of the conductive layer. The method further includes implanting ions into each area of the first set of area. The method further includes forming a second imaging layer over the conductive layer. The method further includes forming openings in the second imaging layer to expose a second set of areas of the conductive layer, wherein the second set of areas is different from the first set of areas. The method further includes implanting ions into the each area of the second set of areas.

Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

Abstract: A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body including a collector region and a base region arranged on top of the collector region, the collector region being doped with dopants of a second doping type and the base region being at least partly doped with dopants of a first doping type and an insulating spacers arranged on top of the base region. The semiconductor body further includes a semiconductor layer including an emitter region arranged on the base region and laterally enclosed by the spacers, the emitter region being doped with dopants of the second doping type forming a pn-junction with the base region, wherein the emitter region is fully located above a horizontal plane through a bottom side of the spacers.

Abstract: Semiconductor devices having vertical field effect transistor (FET) devices with reduced contact resistance are provided, as well as methods for fabricating vertical FET devices with reduced contact resistance. For example, a semiconductor device includes a vertical FET device formed on a substrate, and a vertical source/drain contact. The vertical FET device comprises a first source/drain region disposed on a buried insulating layer of the substrate. The first source/drain region comprises an upper surface, sidewall surfaces, and a bottom surface that contacts the buried insulating layer. The vertical source/drain contact is disposed adjacent to the vertical FET device and contacts at least one sidewall surface of the first source/drain region. The vertical source/drain contact comprises an extended portion which is disposed between the first source/drain region and the buried insulating layer and in contact with at least a portion of the bottom surface of the first source/drain region.

Abstract: A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.

Abstract: The present invention is directed to an STT-MRAM device comprising a plurality of memory elements. Each of the memory elements includes an MTJ structure that comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; a first perpendicular enhancement layer (PEL) formed adjacent to the magnetic free layer structure; a magnetic dead layer formed adjacent to the first PEL; and a magnetic fixed layer exchange coupled to the magnetic reference layer structure through an anti-ferromagnetic coupling layer. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by a second PEL. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.

Abstract: A fin is formed over a first barrier layer over a substrate. The first barrier layer has a band gap greater than the band gap of the fin. In one embodiment, a gate dielectric layer is deposited on the top surface and opposing sidewalls of the fin and is adjacent to a second barrier layer deposited on the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin and an isolating layer is formed adjacent to the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin, and an isolating layer is formed adjacent to the second barrier layer deposited between the fin and the first barrier layer.

Abstract: Provided are a light-emitting diode which prevents degradation of reflectance and which enables high-luminosity light emission, and its manufacturing method. Such a light-emitting diode includes a substrate (1) upon which are provided, in this order, a reflecting layer (6), a transparent film (8) wherein multiple ohmic contact electrodes (7) are embedded at intervals, and a compound semiconductor layer (10) including a current diffusion layer (25) and a light-emitting layer (24) in this order. The periphery of the surface of each ohmic contact electrode (7) on the substrate (1) side are covered by the transparent film (8), and the ohmic contact electrodes (7) contact the reflecting layer (6) and the current diffusion layer (25).

Abstract: A display device includes a plurality of pixels on a substrate including an insulating surface. Each of the plurality of pixels includes: a transistor above the insulating surface; a planarization film covering the transistor; a pixel electrode above the planarization film and electrically connected with the transistor; an insulating layer filled in a recess located around the pixel electrode between the pixels adjacent to each other; a light-emitting layer covering a surface of the pixel electrode and at least a part of a surface of the insulating layer; and a counter electrode above the light-emitting layer. A distance between a surface of the substrate and a face of the light-emitting layer in contact with the insulating layer is equal to or smaller than a distance between the surface of the substrate and a face of the light-emitting layer in contact with the pixel electrode.

Abstract: A technique of reducing the contact resistance between a semiconductor substrate and a metal layer is provided. A manufacturing method of a semiconductor device comprises a process of forming a metal layer on an N surface of a nitride semiconductor substrate. The process of forming the metal layer includes a first process of forming a metal layer by sputtering at a film formation rate controlled to 4 nm/minute or lower.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A dielectric layer is formed over a substrate. An interlayer is formed over the dielectric layer. A first photoresist layer with a first opening is formed over the interlayer and a second photoresist layer having a second opening is formed over the first photoresist layer. Spacers are formed along sidewalls of the first opening and the second opening. A first trench is formed in the interlayer by using the spacer along the first opening as an etch mask. A second trench is formed in the interlayer by using the spacer along the second opening as an etch mask. The first trench and the second trench are extended down into the dielectric layer as a lower portion and an upper portion, respectively, of a dielectric trench.