Abstract: A method of processing a solar cell is disclosed, where a chained patterned ion implant is performed to create a workpiece having a lightly doped surface having more heavily doped regions. This configuration may be used in various embodiments, such as for selective emitter solar cells. Additionally, various mask sets that can be used to create this desired pattern are also disclosed. The mask set may include one or more masks that have an open portion and a patterned portion, where the union of the open portions of the masks comprises the entirety of the surface to be implanted. The patterned portions of the masks combine to create the desired pattern of heavily doped regions.

Abstract: A method for processing a substrate is provided. According to the method, a process gas is supplied to a surface of a substrate, and then a separation gas is supplied to the surface of the substrate. Moreover, a first plasma processing gas is supplied to the surface of the substrate in a first state in which a distance between the first plasma generation unit and the turntable is set at a first distance, and a second plasma processing gas is supplied to the surface of the substrate in a second state in which a distance between the second plasma generation unit and the turntable is set at a second distance shorter than the first distance. Furthermore, the separation gas is supplied to the surface of the substrate.

Abstract: A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.

Abstract: A super-junction semiconductor device includes a junction termination area at a first surface of a semiconductor body and at least partly surrounding an active cell area. An inner part of the junction termination area is arranged between an outer part of the junction termination area and the active cell area. A charge compensation device structure includes first regions of a first conductivity type and second regions of a second conductivity type disposed alternately along a first lateral direction. First surface areas correspond to a projection of the first regions onto the first surface, and second surface areas correspond to a projection of the second regions onto the first surface. The super-junction semiconductor device further includes at least one of a first junction termination extension structure and a second junction termination extension structure.

Abstract: In one embodiment, a semiconductor manufacturing system includes a film forming apparatus configured to form a film on a surface of a wafer. The system further includes a gas supply module configured to supply at least a type of source gas for the film into the film forming apparatus. The system further includes a measurement module configured to measure a discharge amount of an exhaust gas from the film forming apparatus. The system further includes a controller configured to calculate a value corresponding to a surface area of the wafer based on the discharge amount of the exhaust gas from the film forming apparatus, and to control a supply amount of the source gas to the film forming apparatus based on the value corresponding to the surface area of the wafer.

Abstract: In a plasma processing step in a method of manufacturing an element chip in which a plurality of element chips are manufactured by dividing a substrate, which has a plurality of element regions, the substrate is divided into element chips by exposing the substrate to first plasma. In a protection film forming step of forming a protection film covering a side surface and a second surface by exposing the element chips to second plasma of which raw material gas is mixed gas of carbon fluoride and helium, protection film forming conditions are set such that a thickness of a second protection film of the second surface is greater than a thickness of a first protection film of the side surface.

Abstract: Various embodiments may relate to a method for producing an organic optoelectronic component, including forming a first layer on or over a substrate, the substrate including at least one contact pad of the organic optoelectronic component, at least one electrode of the organic optoelectronic component being electrically connected to the at least one contact pad, forming a second layer on or over the first layer, and removing at least the second layer in at least one region of the substrate with the first layer and the contact pad. The adhesion of the substance or of the substance mixture of the first layer on the interface with the substrate is less than the adhesion of the substance or of the substance mixture of the second layer on the interface with the substrate.

Abstract: An embodiment of the present invention provides a manufacturing method of an array substrate comprising forming a gate detecting pattern on the array substrate with gate lines and common electrode lines formed thereon, the gate detecting pattern being arranged on one side of a pixel region of the array substrate and used to connect all the common electrode lines for pixel units; and performing a short circuit or a open circuit detection, wherein if the difference between a signal received by a receiving terminal for a gate line and a signal transmitted from a transmitting terminal for the gate line is larger than a predetermined detection threshold value, it is determined that short circuit between the gate line and a common electrode line or open circuit in the gate line occurs.

Abstract: An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus is provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.

Abstract: Methods for creating barrier layers in a III-V electron channel to reduce band-to-band leakage current and the resulting devices are disclosed. Embodiments include forming a fin channel portion comprising a III-V material, on a barrier layer; forming undoped InP semiconductor spacers at opposite ends of the fin channel portion on the barrier layer; forming S/D regions adjacent the undoped InP semiconductor spacers on the barrier layer; and forming a high-k/metal gate over the fin channel portion and undoped InP semiconductor spacers.

Abstract: The present invention provides a method for manufacturing an SOI wafer including a step of forming an insulator film on an entire surface of a bond wafer before bonding, bringing a bonded wafer before delaminating the bond wafer at an ion implanted layer into contact with a liquid that enables dissolving the insulator film while protecting the insulator film on a back surface on the opposite side of a bonding surface of the bond wafer, or exposing the bonded wafer to a gas that enables dissolving the insulator film, and thus etching the insulator film placed between the bond wafer and a base wafer from an outer peripheral end of the bonded wafer toward a center of the bonded wafer.

Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.

Abstract: The present invention provides a method for forming a semiconductor structure, at least including the following steps: first, four sacrificial patterns are formed on a substrate, and a plurality of spacers are then formed surrounding each sacrificial pattern. Next, the four sacrificial patterns are removed, and a photoresist layer is formed between each spacer, covering parts of each spacer. Afterwards, a first etching process is performed to partially remove each spacer, and the photoresist layer is then removed, and a second etching process is then performed, to remove each spacer again, and to form four nanowire hard masks.

Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.

Abstract: Embodiments of the disclosure generally relate to a support cylinder used in a thermal process chamber. In one embodiment, the support cylinder includes a hollow cylindrical body comprising an inner peripheral surface, an outer peripheral surface parallel to the inner peripheral surface, wherein the inner peripheral surface and the outer peripheral surface extend along a direction parallel to a longitudinal axis of the support cylinder, and a lateral portion extending radially from the outer peripheral surface to the inner peripheral surface, wherein the lateral portion comprises a first end having a first beveled portion, a first rounded portion, and a first planar portion connecting the first beveled portion and the first rounded portion, and a second end opposing the first end, the second end having a second beveled portion, a second rounded portion, and a second planar portion connecting the second beveled portion and the second rounded portion.

Abstract: Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping.

Abstract: After forming a plurality of first semiconductor fins having a first spacing in a logic device region and a plurality of second semiconductor fins having a second spacing in a memory device region, sacrificial spacers are formed on sidewalls of the plurality of the first semiconductor fins and the plurality of the second semiconductor fins to completely fill spaces between the plurality of first semiconductor fins, but only partially fill spaces between second semiconductor fins. Next, dielectric barrier layer portions are formed in gaps between the sacrificial spacers. After removal of the sacrificial spacers, an entirety of the plurality of first semiconductor fins is laterally enclosed by a corresponding pair of neighboring dielectric barrier layers, while each of the plurality of second semiconductor fins is laterally enclosed by a corresponding pair of neighboring dielectric barrier layer portions.

Abstract: A method of fabricating a fin for a FinFET device includes providing a semiconductor substrate, forming a patterned silicon germanium layer on the semiconductor substrate, epitaxially growing a silicon layer on a top surface and sidewalls of the patterned silicon germanium layer, forming a sacrificial layer covering the patterned silicon germanium layer, and removing the sacrificial layer and a portion of the silicon layer disposed on the top surface of the patterned silicon germanium layer until a top surface of the sacrificial layer is co-planar with the top surface of the patterned silicon germanium layer. The method further includes removing the patterned silicon germanium layer and removing the sacrificial layer to form the fin. The epitaxially formed fin does not have the issues of line width roughness and edge roughness to improve the performance of the FinFET device.

Abstract: The present techniques provide a method for producing a Group III nitride semiconductor light-emitting device, with suppression of an increase in polarity inversion defect density. The production method includes an n-type semiconductor layer formation step, a light-emitting layer formation step, and a p-type semiconductor layer formation step. The p-type semiconductor layer formation step includes a p-type cladding layer formation step. The p-type cladding layer formation step includes a first p-type semiconductor layer formation step for forming a p-type AlGaN layer, a first semiconductor layer growth intermission step after the first p-type semiconductor layer formation step, and a p-type InGaN layer formation step after the first semiconductor layer growth intermission step. In the first semiconductor layer growth intermission step, a mixture of nitrogen gas and hydrogen gas is supplied to the substrate.

Abstract: Disclosed herein are 3D NAND memory devices having an oxide semiconductor vertical NAND channel and methods for forming the same. The oxide semiconductor may have a crystalline structure. The channel of the vertically-oriented NAND string may be cylindrically shaped. The crystalline structure has an axis that may be aligned crystalline with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically-oriented channel. The crystalline structure may have a first axis that is aligned parallel to the vertical channel, a second axis that is aligned perpendicular to a surface of the cylindrically shaped channel, etc.