Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port in the input mode, the multi-address read operation including receiving a first address and a second address using the at least one signal line in the input mode before switching to the output mode, switching to the output mode and outputting data identified by the first address using the at least one signal line.

Abstract: Data is synchronized when transmitted from a circuit operated at first frequency to another circuit operated at second frequency. A synchronization method includes storing data write pointers in a line, storing data input from a source at first frequency at a location in a data buffer designated by the write pointer at one end of the line, taking out the write pointer at the one end from the line to store it in the synchronization buffer, synchronizing a validation signal input from the input source at first frequency to second frequency, reading out the write pointer stored in the synchronization buffer when the validation signal is synchronized, adding completion information that indicates completion of synchronization to the data stored at the location in the data buffer designated by the read out write pointer, and reading out, from the data buffer, the data to which the completion information is added.

Abstract: Fuse programming circuits, devices and methods. In some embodiments, a fuse circuit can include a fuse pad configured to receive a voltage, a fuse having a first end coupled to the fuse pad and a second end coupled to a switching element configured to enable a current to pass from the fuse pad to a ground potential.

Abstract: According to one embodiment, a memory system includes a plurality of memory packages, on-die termination (ODT) circuits, and a controller. The plurality of memory packages are coupled by a common bus and arranged in groups, each group includes a pair of memory packages facing each other, and each memory package includes a plurality of memory chips. The ODT circuits are respectively disposed in the memory packages. The ODT circuits are on/off controlled based on an asserted state of a chip enable signal CEn acquired using a periodic signal of at least two cycles.

Abstract: An integrated circuit device includes a plurality of word lines, a string selection line structure stacked on the plurality of word lines, and a plurality of channel structures extending in a vertical direction through the plurality of word lines and the string selection line structure. The string selection line structure includes a string selection bent line including a lower horizontal extension portion extending in a horizontal direction at a first level higher than the plurality of word lines, an upper horizontal extension portion extending in the horizontal direction at a second level higher than the first level, and a vertical extension portion connected between the lower horizontal extension portion and the upper horizontal extension portion.

Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

Abstract: A circuit includes an OTP cell, an NVM cell, and a bit line coupled to the OTP cell, the NVM cell, and a first input terminal of an amplifier. The amplifier is configured to generate an output voltage based on a signal on the bit line, an ADC is configured to generate a digital output signal based on the output voltage, and a comparator includes a first input port coupled to an output port of the ADC and is configured to output a data bit responsive to a comparison of the digital output signal to a threshold level received at a second input port.

Abstract: A data transceiver device and an operation method are provided. The data transceiver device receives input data and transmits output data. The data transceiver device includes a buffer circuit, a storage circuit, a timing circuit and a control circuit. The buffer circuit is configured to store input data. The storage circuit is configured to store the output data. The timing circuit is configured to generate a time-out signal according to the set time. The control circuit is configured to process the input data to generate the output data, to store the output data in the storage circuit, and to transmit the output data according to an output data threshold value and the time-out signal. The control circuit adjusts the set time and/or the output data threshold value based on an initial condition and the state of the buffer circuit.

Abstract: A data driving circuit may include a trigger circuit and a pre-driver. The trigger circuit may be configured to block a remaining signal path among a plurality of signal paths for transmitting data except for a signal path corresponding to a currently selected driving strength. The pre-driver may be configured to drive data, which are transmitted through the signal path corresponding to the currently selected driving strength, using an impedance determined in accordance with a plurality of impedance control codes.

Abstract: Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the inning for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.

Abstract: The purpose of the invention is to compensate for the radiation tolerance of a semiconductor memory. An apparatus (10) for compensating for radiation tolerance comprises: a voltage value acquisition unit (11) that acquires a data retention voltage value that is a maximum voltage value at which data is inverted when a power supply voltage of a semiconductor memory having a latch circuit is lowered; a correction value determination unit (12) that determines a voltage correction value on the basis of a difference between the data retention voltage value and a reference voltage value; and a voltage adjustment unit (13) that adjusts at least one among the power supply voltage and a substrate bias voltage by using the voltage correction value. The reference voltage value is set to be equal to or lower than the data retention voltage value that satisfies a required radiation tolerance.

Abstract: An electrochemical device includes an electrochemical cell and an electric circuit. The electrochemical cell comprises a first solid component and a second solid component. The two solid components comprise same chemical elements but have different concentrations of at least one type of the chemical elements. A solid electrolyte is arranged between the two solid components. The solid electrolyte is a dielectric material. The electric circuit is connected to the electrochemical cell. The electrochemical cell may be operated according to a redox process, so as to exchange chemical elements of the at least one type between the first solid component and the second solid component and thereby change an electrical conductance of each of the two solid components.

Abstract: Methods and apparatuses with counter-based reading are described. In a memory device, a memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.

Abstract: Embodiments provide a write operation circuit, a semiconductor memory, and write operation method. The write operation circuit includes: a data determination module that determines whether to flip an input data of the semiconductor memory depending on the number of high data bits in the input data so as to generate a flip flag data and a first intermediate data; a data buffer module that determines whether to flip a global bus according to a second intermediate data, where the second intermediate data is an inverted data of the first intermediate data; a data receiving module that decodes the global bus data according to the flip flag data and writes the decoded data into a memory bank of the semiconductor, where the decoding including determining whether to flip the global bus data; and a precharge module that sets the initial state of the global bus to low.

Abstract: According to one embodiment, a shift register memory includes blocks and a control circuit. The blocks each includes data storing shift strings. Each of the data storing shift strings includes layers. The control circuit performs storing and reading data by shifting one layer of the layers, in a direction along each of the data storing shift strings. The reading includes reading data from a first layer of the layers. The storing includes storing data to a second layer of the layers. The control circuit reads first data stored in one or more third layers of the layers, the one or more third layers being successive from the first layer, determines a shift parameter in accordance with the reading of the first data, and performs the reading using the determined shift parameter.

Abstract: A method for determining an optimal threshold of a nonvolatile memory device, the method including: reading a page from a nonvolatile memory device with a default threshold and attempting to hard decode the page using the default threshold; reading the page two more times with a predetermined offset voltage when the hard decoding fails and attempting to soft decode the page using the default threshold; approximating an empirical distribution of successfully decoded bits with a Gaussian distribution for each level; finding an intersection of the Gaussian distributions; and setting the intersection as a new reading threshold and reading the page again with the new reading threshold.

Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

Abstract: A memory controller, a method for read control of a memory, and an associated storage system are provided. The memory controller includes a data latch circuit, a mask generating circuit, a clock control logic electrically coupled to the mask generating circuit, and a demultiplexer electrically coupled to the data latch circuit and the clock control logic. The data latch circuit latches a series of data within a data signal from the memory according to a data strobe signal from the memory. The mask generating circuit generates a mask signal according to the data strobe signal. The clock control logic generates a receiving clock signal according to the mask signal. The demultiplexer determines valid data within the series of data with aid of the receiving clock signal.