Abstract: The disclosed technology teaches a memory device with memory cells, each with a sense circuit with an input node in current flow communication, a BLC transistor, a transfer transistor, a current source transistor, and an output circuit to generate data based on a voltage on the sensing node. Also disclosed is a sensing sequence in which control circuits apply BLC voltage to the BLC transistor, transfer voltage to the transfer transistor and current control voltage to the current source transistor to provide a charging current to the BL, and to adjust the current control voltage to provide a keeping current on the BL from the current source transistor, and to apply a read voltage to a selected memory cell on the bit line. Additionally included is applying a timing signal to the output circuit to generate the data based on a voltage on the sensing node.

Abstract: The present disclosure provides a fuse storage cell. The fuse storage cell includes a transistor and N fuse elements. The transistor includes a source, a drain, and a gate. Each fuse element of the N fuse elements includes a first terminal and a second terminal. The first terminal of the fuse element is electrically connected to the drain of the transistor, and the second terminal of the fuse is configured for inputting a read voltage or a programming voltage. N is a positive integer.

Abstract: The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.

Abstract: A variable low-resistance line memory device and an operating method thereof are provided. The memory device includes: a base including a spontaneous polarizable material; a gate arranged adjacent to the base; at least two polarization regions formed in the base by applying an electric field to the base through the gate, the at least two polarization regions having polarization in different directions from each other; a variable low-resistance line corresponding to a boundary between the at least two polarization regions selectively having polarization in different directions from each other; a source located to contact the variable low-resistance line; and a drain located to contact the variable low-resistance line, wherein the variable low-resistance line is formed in a region of the base, the region having a lower electrical resistance than other regions of the base adjacent to the variable low-resistance line.

Abstract: A device comprises a column of cells disposed in multiple levels of word lines including a pillar comprising a first vertical conductive line, a second vertical conductive line, and a vertical semiconductor body disposed between and in contact with the first and second vertical conductive lines. A pillar select line is adjacent to and separated by a gate dielectric from the vertical semiconductor body to form a pillar select switch, the pillar select line disposed beneath the first and second vertical conductive lines. A bottom select line is disposed beneath the first and second vertical conductive lines and insulated from the pillar select line and the first and second vertical conductive lines. The bottom select line is in current-flow contact with the vertical semiconductor body of the pillar.

Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.

Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

Abstract: A memory cell includes a semiconductor substrate, a transistor, and a first anti-fuse structure. The transistor is above the semiconductor substrate. The first anti-fuse structure is above the semiconductor substrate and adjacent the transistor, and includes a first terminal and a second terminal. The first terminal of the first anti-fuse structure is in the semiconductor substrate and laterally surrounds the transistor. The second terminal of the first anti-fuse structure is above and spaced apart from the first terminal of the first anti-fuse structure.

Abstract: The present application discloses a programmable memory, wherein an anti-fuse unit thereof is formed by adding an efuse between an anti-fuse programming transistor and a control transistor of a conventional anti-fuse unit such that the anti-fuse unit can be programmed twice, that is, normal programming can be implemented by breaking down a gate-source insulation layer of the anti-fuse programming transistor, and correction programming can be further implemented by fusing the efuse such that correction programming can be performed on a normal programming result, thereby changing a logical state of the normally programmed anti-fuse unit. For the programmable memory, a reprogramming method can be directly used to correct an error bit, thereby simplifying circuit and layout designs, resulting in a smaller layout area and higher reliability, increasing the applicability and flexibility, while retaining original features of reliable and safe data of the anti-fuse unit.

Abstract: Programming a fuse for a one-time programmable (OTP) memory can require applying a programming current for a programming period to increase a resistance of the fuse. It may be desirable for the resistance to be very high. A very high resistance may be achieved by applying a high programming current to form a void in the fuse. Applying the high programming current too long after the void is formed, however, may lead to uncontrolled variations and ultimately damage. Accordingly, it may be desirable to end the programming period sometime after the void is formed but before the uncontrolled variations begin. Ideally the programming period is ended at a time at which the programming current is minimum. The disclosed circuits and method provide a means to estimate this time without requiring the complexity of sensing very low levels of programming current.

Abstract: A memory device to estimate signal and noise characteristics of a group of memory cells in response to a command identifying the group of memory cells. For example, the memory device measures first signal and noise characteristics of the group of memory cells based on first test voltages, compute using the first signal and noise characteristics an optimized read voltage of the group of memory cells, and estimate, using the first signal and noise characteristics, second signal and noise characteristics of the group of memory cells, where the second signal and noise characteristics are based on second test voltages that are centered at the optimized read voltage of the group of memory cells.

Abstract: There are provided a data buffer and a memory system having the same. The data buffer includes first and second amplifiers configured to output output data by inverting input data, the first and second amplifiers having coupled output nodes to which the output data is output, wherein both of the first and second amplifiers are activated to output the output data when the input data has a first swing level, and wherein one of the first and second amplifiers is activated to output the output data when the input data has a second swing level narrower than the first swing level.

Abstract: Methods, systems, and devices related to identifying high impedance faults in a memory device are described. A memory device may perform a first write operation to write a first logic state to a memory cell. During the first write operation, the memory device may establish a connection between a supply line and a control line associated with applying an output of a driver of a digit line coupled to the memory cell. After performing the first operation, the memory device may configure the supply line in a floating state. After the supply line is floated, the memory device may perform a second write operation to write a second logic state to the memory cell. The memory device may perform a third operation for reading the memory cell. The memory device may determine the condition of the supply line or control based on the result of the read operation.

Abstract: Methods, systems, and devices for distribution-following access operations for a memory device are described. In an example, the described techniques may include identifying an activation of a first memory cell at a first condition of a biasing operation, and identifying an activation of a second memory cell at a second condition of the biasing operation, and determining a parameter of an access operation based at least in part on a difference between the first condition and the second condition. In some examples, the memory cells may be associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Abstract: Ternary content addressable memory (TCAM) circuits are provided herein. In one example implementation, a TCAM circuit can include a first spin-orbit torque (SOT) magnetic tunnel junction (MTJ) element having a pinned layer coupled to a first read transistor controlled by a first search line, and having a spin hall effect (SHE) layer coupled in a first configuration across complemented write inputs. The TCAM circuit can include a second SOT MTJ element having a pinned layer coupled to a second read transistor controlled by a second search line, and having a SHE layer coupled in a second configuration across the complemented write inputs. The TCAM circuit can include a bias transistor configured to provide a bias voltage to drain terminals of the first read transistor and the second read transistor, and a voltage keeper element that couples the drain terminals to a match indicator line.

Abstract: Apparatuses, systems, and methods for fuse based device identification. A device may include a number of fuses which are used to encode permanent information on the device. The device may receive an identification request, and may generate an identification number based on the states of at least a portion of the fuses. For example, the device may include a hash generator, which may generate the identification number by using the fuse information as a seed for a hash algorithm.

Abstract: A method includes performing a first read operation on a memory cell of a programmed first one-time programmable (OTP) anti-fuse to determine a state of the memory cell based on a first parameter level, performing a second read operation on the memory cell of the programmed first OTP anti-fuse to determine the state of the memory cell based on a second parameter level, identifying the memory cell of the first OTP anti-fuse as an uncertain bit when the state determined during the first read operation and the state determined during the second read operation are different, and programing one or more memory cells of a second OTP anti-fuse based on a bit position of the identified uncertain bit of the first OTP anti-fuse.

Abstract: In order to eliminate an increase in the source potential of a transistor selected during writing or reading, this semiconductor device is equipped with: a variable-resistance type first switch having a first terminal and a second terminal; a variable-resistance type second switch having a third terminal and a fourth terminal, the third terminal being connected to the second terminal to form an intermediate node; first wiring connected to the first terminal; second wiring connected to the fourth terminal and, in a planar view, extending in a direction crossing the first wiring; a first selection transistor connected to the first wiring; a second selection transistor connected to the second wiring; a first well terminal connection line to which a well terminal of the first selection transistor is connected; and a second well terminal connection line to which a well terminal of the second selection transistor is connected.

Abstract: A self-biased sense amplification circuit includes a local bit line, a reset unit, a main bit lie, a pre-amplifier, a data line, a sample reference unit, and a sense amplifier. The local bit line receives a cell current generated by a memory cell during a sense operation. The reset unit resets the local bit line to a first system voltage during a sample operation. The pre-amplifier generates a read current on the main bit line according to a voltage of the local bit line during the sample operation and the sense operation. The data line is coupled to the main bit line. The sample reference unit generates a first reference current and a second reference current during the sample operation, and generates the first reference current during the sense operation. The sense amplifier senses a voltage of the data line.