Abstract: A method and an apparatus for implementing a semiconductor switch multi-stage drive circuit. The disclosed method and an apparatus reduce losses in a semiconductor switch when it is turned from an off state to an on state or from an on state to an off state. The reduction in losses is achieved without influencing the dv/dt across the semiconductor switch during a first time period while the semiconductor switch is switching. This reduction in losses is therefore achieved with very little increase in the noise generated due to rapid dv/dt during the first time period when the semiconductor switch is switching. The configuration of the circuitry to achieve this reduction in switching losses is such that benefits are less sensitive to manufacturing tolerances and temperature effects than alternative semiconductor switch drive schemes to achieve similar results.

Abstract: A semiconductor device having a sense amplifier driver with a capacitor affected by off current is provided. The sense amplifier driver, which receives a clock signal and generates a sense amplifier enable signal by buffering the clock signal, includes a plurality of inverters connected in series and at least one capacitor. A PMOS transistor of at least a first inverter of the plurality of inverters is connected between a dummy bit line, in which voltage drop by the off current is generated, and the output terminal of the first inverter and the at least one capacitor is connected between the dummy bit line and the output terminal of a second inverter which inverts an output signal of the first inverter. Therefore, the capacitance of the at least one capacitor is determined by voltage of the dummy bit line. Therefore, since the voltage drop of the dummy bit line is larger when the magnitude of the off current is larger, the capacitance of the at least one capacitor is larger.

Abstract: A charge sampling circuit, having a control signal generator for controlling an analog input signal to the charge sampling circuit to be integrated by an integrator during a sampling phase responsive to a sampling signal from the control signal generator is presented. The current of the analog input signal is integrated to an integrated charge for producing one of a proportional voltage and current sample at a signal output at the end of the sampling phase.

Abstract: Binary hysteresis comparator circuits, methods, and applications. A binary constant defines a window within which a binary input can change its value without triggering the comparator circuit output signal. An exemplary binary hysteresis comparator circuit includes a comparator circuit, an adder circuit, and a multiplexer circuit. The comparator circuit compares two multi-bit input values. A first comparator input is provided by the multiplexer circuit, which selects either a first value or a second value, depending on the comparator output signal. The first and second values differ by the binary constant, which is added to or subtracted from a multi-bit circuit input value by the adder circuit. An increase (or decrease) of less than the binary constant is ignored. Some embodiments include an optional overflow prevention circuit that prevents the selected value from exceeding predetermined parameters.

Abstract: A track-and-hold peak detector circuit, which can operate at low input signal frequencies, includes a capacitor to hold a peak voltage of the input signal and logic circuitry that reduces an effect of leakage current into or out of the capacitor, and therefore, provides protection against self-switching of an output signal of the peak detector circuit.

Abstract: Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier having a number of first stage input and output ports. The first stage amplifier is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals. Also included are a number of second stage amplifiers, each having second stage input and output ports, the second stage input ports being respectively coupled to the first stage output ports and being configured to receive the number of output signals. A gain control device is coupled to at least one from the group including the first stage input ports, the first stage output ports, and the second stage output ports. The gain control device is also configured to control a gain of at least one of the first stage amplifier and one or more of the number of second stage amplifiers.

Abstract: A delay locked loop for use in an integrated circuit device includes a coarse delay chain in series with a micro-stepped delay chain. The coarse delay chain includes a plurality of coarse delay units configured for selectively providing a coarse delay with respect to an input clock signal, and the micro-stepped delay chain is configured for selectively providing a fine delay adjustment with respect to the input clock signal. The micro-stepped delay chain further includes a plurality of parallel signal paths, wherein one or more of the parallel signal paths are capacitively loaded so as to provide the fine delay adjustment.

Abstract: The invention provides a sense amplifier apparatus (100) for bit line signals (103, 104) having a bit line pair which comprises two bit lines (107, 108) to which complementary bit line signals (103, 104) are applied, and a switching device (101) which is connected cross-coupled between the bit line, with a first transistor pair (201, 202) and a second transistor pair (105, 106), with the switching device having a switching transistor pair which comprises two transistors (205; 206) connected in series with the first transistors (201; 202), in which a switching signal (207) can be applied to the gates of the switching transistors (205; 206) and, furthermore, a holding device (102) being connected between the bit lines (107, 108) and maintaining the levels, which are switched by the switching device (101), on the bit line signals (103, 104) which are applied to the bit lines (107, 108).

Abstract: In order to improve the efficiency of a driver circuit for controlling upper and lower switching means (T3, T4) for converting a direct voltage Ud into a clocked output voltage Ua for a resonant converter with a high-voltage section (HT) for controlling the upper switching means (T3) and a low-voltage section (NT) for controlling the lower switching means (T4), which switch the switching means (T3, T4) on alternately to one another, the switch-on phases of the switching means (T3, T4) being separated from one another by dead-time phases, there is provided a first circuit section which controls the duty cycle ?tein3 of the upper switching means (T3) as a function of the duty cycle ?tein4 of the lower switching means (T4), and receives control signals from the low-voltage section (NT) exclusively during the duty cycle ?tein4 of the lower switching means (T4).

Abstract: Embodiments of the invention provide a method and an apparatus for generating a total harmonic distortion reference signal. A triangle wave having a predetermined frequency and a predetermined amplitude is generated. The triangle wave is filtered to produce a signal substantially consisting of a sinusoid at the predetermined frequency and selected harmonics of predetermined amplitudes.

Abstract: A power up signal generator includes a signal converter for converting an applied external source voltage to a voltage applied at a trigger node when the external source voltage rises to a first threshold, and a current source for flowing a reference current from the trigger node. A first inverter connected to the trigger node outputs a low level signal when the trigger node voltage reaches a second threshold. A second inverter outputs a power up signal after receiving the low level signal from the first inverter. The signal converter may include a PMOS transistor configuration, such that the trip voltage of the power up signal generator is dependent only on a single MOSFET transistor threshold voltage.

Abstract: An I/O driver includes a pull-down module and pull-up module. The pull-down module has one or more NMOS transistors serially coupled between ground and an output node. The pull-up module has one or more PMOS transistors serially coupled between a first voltage and the output node. The gates of the PMOS and NMOS transistors are controlled by a set of differential biases for selectively pulling the output node to the first voltage or ground. The differential biases are separately set for each of the transistors so that a voltage difference across each of the transistors does not exceed a predetermined value, thereby preventing the same from damage.

Abstract: A receiver and receiver front end having multiple independent differential inputs, multiple independent differential low-noise amplifiers, and two sets of double-balanced IQ mixers. The double-balanced mixers include cross-coupled PMOS devices that dynamically inject current at zero-crossing points to cancel out tail currents in the mixers. Also, methods of operating the above-discussed receiver and receiver front end.

Abstract: A compensation apparatus maintains an effective resistance of one or more resistors in a circuit by associating an adjustable resistor circuit to each resistor. The compensation apparatus compares the resistance of a resistor in the circuit with the resistance of a reference resistor. When the resistance of the resistor in the circuit falls outside of a desired range, the compensation apparatus adjusts the resistance of the adjustable resistor to adjust the effective resistance of the resistor and adjustable resistor combination.

Abstract: An apparatus includes a circuit having first and second portions which are each coupled between first and second nodes. The first portion includes a resonant tunneling device, and the second portion has a reactance that includes, at a selected frequency, a complex conjugate reactance of a reactance of the resonant tunneling device. The complex conjugate reactance substantially cancels the reactance of the resonant tunneling device at the selected frequency.

Abstract: A system and method for a programmable threshold detector. A programmable threshold detector circuit is described comprising an offset current generator circuit, a comparator circuit, a programmable delay circuit, and a counter timer coupled together. The offset current generator circuit generates a programmable offset current that is associated with a programmable offset voltage. The comparator circuit compares an input signal to a programmable offset voltage. The programmable delay circuit provides a capacitance controlled time delay before asserting a standby mode for the device when the input signal is less than the programmable offset voltage. The counter timer provides a counter controlled time delay before deasserting the standby mode when the input signal is greater than the programmable offset voltage.

Abstract: A driving circuit for electrical nailing gun is disclosed to include a capacitive charging/discharging unit formed of a first resistor, a first diode, and a capacitor connected in series and connected with two opposite ends thereof to the positive and negative poles of AC power source, an excited field unit formed of a first coil and a first electrically-controlled switch connected in series and having two opposite ends connected in parallel to the capacitor, and a control unit electrically connected to the first electrically-controlled switch for activating the first electrically-controlled switch.

Abstract: A novel output buffer circuit including an input circuit, a voltage generating circuit, and an output circuit forms a three-state buffer circuit. The output circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. With such a configuration, a simple circuit using no high voltage insulated transistors and level shift circuits can be made, and the simple circuit can output either a low voltage signal or a high voltage signal responsive to a low voltage input signal, reduce the manufacturing cost and the delay of the risetime of the output signal, which are associated with a high voltage insulated transistor. Furthermore, cost can be reduced by miniaturization of the circuit size.

Abstract: A high voltage AC power supply circuit for a capacitive load CL, such as an electroluminescent lamp, includes a low voltage DC supply, an inductor L and a FET S in series. The FET S can be pulsed so that the inductor L generates a voltage to charge the capacitive load CL via an H-bridge H, which is in parallel with the FET S. A diode D prevents current discharging from the capacitive load CL while the FET S is closed. The total capacitance downstream of the diode D and in parallel with the capacitive load CL is less than the capacitive load CL, so that when the polarity of the H-bridge is reversed, the voltage across the H-bridge collapses to earth and the capacitive load CL is discharged via the low voltage DC supply. The circuits which a employ a large smoothing capacitor in parallel with the H-bridge.

Abstract: The present invention provides a system for limiting energy levels across the output of a driver circuitry segment (100). The system provides an output structure (102) adapted to drive an output load (104). A transconductance component (106) is communicatively coupled to the output structure, and adapted to output a transconductance current that is proportional to the voltage across the output structure. A scaling component (108) is communicatively coupled to the output structure, and adapted to output a scaled current that is proportional, by some scaling factor, to the current through the output structure. A qualifying component (110) is communicatively coupled to the scaling component, and adapted to activate a trigger component (112) when the scaled current passes a first threshold. The trigger component is communicatively coupled to the qualifying component, the transconductance component, and the output structure.