Abstract: A trimming structure for trimming functional parameters of an Integrated Circuit—IC—(100) includes a first (115a) and at least one second functional blocks (115b, . . . ,115n) with which a first (Vrg,a) and at least one second IC functional parameters (Vrg,b, . . . ,Vrg,n) are respectively associated. The trimming structure includes respective trimmable circuit structures (205a,210a, . . . ,205n,210n) included in the first and at least one second functional blocks, and trimming configuration storage (110) for storing trimming configurations for the trimmable circuit structures. A change in the trimming configuration of the first functional block causes a corresponding change in the trimming configuration of the second functional block.

Abstract: In a driver circuit of a display device, an electric potential difference between high-level power supply voltage VDD and low-level power supply voltage VSS2 in shift registers and buffers is set smaller than an electric potential difference between high-level voltage VDD and low-level voltage VSS of enable signals OE in order to prevent increase in voltage stress on each transistor and concurrently to make larger an electric potential difference between high-level voltage and low-level voltage of output signals.

Abstract: A method and apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is implemented to measure the period of a reference signal and to mirror the period into a second delay line such that an adjusted reference signal having a frequency approximately equal to the frequency of the reference clock may be generated. The adjusted reference signal is delivered to an oscillator such that the oscillator begins oscillating at approximately the same frequency as the reference clock signal to provide a fast locking synchronization device.

Abstract: First, second and third current generators, and first and second switching devices are provided. Current values of the first and second current generators are equal to each other and a current value of the third current generator is twice as large as the current value of the first and second current generators. The first current generator and the third current generator are connected to each other through the first switching device, and the second current generator and the third current generator are connected to each other through the second switching device. A first output is taken out from a node between the first switching device and the first current generator, and a second output is taken out from a node between the second switching device and the second current generator.

Abstract: The present invention relates to a booster circuit of a non-volatile memory requiring a plus or minus high voltage equal to or higher than a power-supply voltage. The present invention can generate a high voltage of approximately 12 V even at a low power-supply voltage equal to or lower than 3 V and generate not only a plus high voltage but also a minus high voltage by the same circuit. Also, by combining a body-controlled type parallel charge pump, which is a booster circuit according to the present invention, with a serial-type charge pump, two types of high voltages can be efficiently generated and a reduction in chip areas can be achieved.

Abstract: A clamping circuit including a current mirror circuit including transistors constituting a mirror pair disposed at ground side, each of the transistors being connected to a power source through a resistance element; a plurality of adjusting transistors connected in parallel to a first transistor as one transistor of the current mirror circuit at a side for determining mirror current flowing in the current mirror circuit; a plurality of switch circuits that are respectively connected to conduction control terminals of the plural adjusting transistors in connection with one another and control the conduction states of the corresponding adjusting transistors; and a clamping transistor that has a conduction control terminal connected to a power source side terminal of a second transistor as the other transistor of the mirror pair, and clamps a voltage applied to a clamp terminal with the potential of the conduction control terminal as a reference.

Abstract: The present invention disclosed herein is a high voltage generator circuit. The high voltage generator circuit includes a charge pump and a pump clock signal generator. The pump clock signal is gated to the charge pump when the high voltage is below a target voltage. After the high voltage reaches the target voltage, the high voltage cyclically falls below the target voltage. After the high voltage reaches the target voltage, a pump clock generator block circuit limits the transmission of the pump clock signal so that only N clock signals are gate to the charge pump each cycle, where N is the number one or greater.

Abstract: Methods and systems for measuring temperature are described. A voltage source supplies a voltage. A current source supplies an amount of current that is controlled using a digital input signal. A diode is coupled to the current source. A comparator has a first input coupled to the voltage source and a second input coupled to a node between the current source and the diode. The digital input signal is changed to a value that causes an output of the comparator to change state. A value of the digital input signal is determined for each of two voltages. The values of the digital input signal and the two voltage values (or the difference between the two voltages) are used as inputs to a temperature calculation.

Abstract: By flexibly coping with both image sensors of a CCD sensor and a CMOS sensor without providing any external circuit, a signal processing is performed. In a sensor selecting switch provided in an image-sensor signal-processing circuit, first and fourth switches are turned on when the CMOS sensor is connected, and second and third switches are turned on when the CCD sensor is connected. The sensor selecting switch is controlled by a control signal generated in a control circuit, based on sensor selection data which is stored in a register and which is data for selecting the CCD or CMOS sensor. By so doing, even if polarity of an output signal of the image sensor is reversed, a normal signal is inputted to both inputs of the CDS amplifier, whereby it is possible to flexibly cope with both of the CCD and CMOS sensors.

Abstract: A sampling circuit for compensating the phase difference of a sampling pulse due to a temperature variation to accurately sample input signals is provided. The sampling circuit samples received input signals. The sampling circuit includes a pulse generator for generating a pulse signal according to a timing at which an input signal should be sampled, a step recovery diode for outputting a sampling pulse responsive to the pulse signal, a detector for detecting the value for the input signal according to the sampling pulse, a temperature detecting circuit for detecting the temperature around the step recovery diode and a temperature compensating unit for controlling a timing at which the step recovery diode outputs the sampling pulse based on the temperature detected by the temperature detecting circuit.

Abstract: A power supply switching circuit includes an input terminal (2) for receiving a signal from a motherboard, an output terminal (4) to output a control signal, a first Bipolar Junction Transistor (BJT) (5), and a second BJT (7). A base of the first BJT is connected to the input terminal via a base bleeder circuit. A collector of the first BJT is connected to a stand-by power supply terminal (10) via a collector resistor. A base of the second BJT is connected to the collector of the first BJT. A collector of the second BJT is connected to a system power supply terminal (12) via a collector resistor. The collector of the second BJT is connected to the output terminal. Emitters of the first and second BJTs are grounded.

Abstract: A level shifting circuit with a power monitor enable for mixed-voltage applications is described. The level shifter translates signals from a first power supply voltage domain to a second. The level shifter provides a known output state, rather than an undefined mid-rail state, when either of the power supplies for the voltage domains is not adequately powered. In addition, the level shifter is IDDQ (quiescent current) compliant when static, drawing negligible current from the power supply. The level shifter can be used with a power monitor circuit, which controls the level shifter during power-up with an enable signal.

Abstract: A current loop drive module includes a drive circuit and a compliance voltage controller. The drive circuit is configured to receive a compliance voltage and operable to generate a current loop signal based on the compliance voltage for receipt by an associated load coupled to the drive circuit. The compliance voltage controller is operable to adjust the compliance voltage based on the associated load. A method for generating a current loop signal includes generating a current loop signal based on a compliance voltage for receipt by an associated load and adjusting the compliance voltage based on the associated load.

Abstract: A control circuit for an inductive load driver includes a control block activated by a trigger signal and an output coupled to the control terminal of a power element. The control circuit includes an auxiliary current generator capable of delivering a current that is added to the current provided by control block and the sum of these currents is provided to the control terminal of the power element. The auxiliary current generator enables the inductive load driver to operate normally even though the trigger voltage is less than an optimal voltage value.

Abstract: Analog control integrated FET based variable resistors and attenuators using the variable resistors having a wide range of monotonic and substantially linear attenuation with control voltage for use in circuits having AC signals of AC signal frequencies. The variable resistors comprise field effect devices (FETs) biased to operate in their linear region and having their bodies and gates coupled to a reference voltage and a control voltage, respectively, through impedances, typically resistors, having impedances that are higher than the impedances of parasitic capacitances at the signal frequencies. This allows the body and gate of each FET to vary in voltage with the signal to maintain the bias of the FETs in the presence of large signals. Various embodiments are disclosed.

Abstract: A signal detector circuit and digital signal receiver implementing the same. In one embodiment the digital signal receiver includes a switch point detector having a detector output and including a transistor array comprising one or more pull-up branches and one or more pull-down branches. A switch point control circuit is coupled to the switch point detector. The switch point control circuit generates branch enable signals for selectively enabling or disabling said one or more pull-up branches and said one or more pull-down branches in a detector output polarity dependent manner.

Abstract: The invention concerns a circuit (1) for storing a binary code (B1, B2, Bi-1, Bi, Bn-1, Bn) in an integrated circuit chip, comprising an input terminal (2) applying a signal (E) triggering reading of the code, output terminals (31, 32, 3i-1, 3i, 3n-1, 3n) for delivering said binary code, first electrical paths (P1, P2, Pi, Pn) individually connecting said input terminal to each output terminal, each path inputting a fixed delay in the manufacture of the integrated circuit, and means (4, 51, 52, 5i, 5n) simultaneously integrating the binary states present in output of the electrical paths.

Abstract: An active diode including a NMOS transistor having a source terminal, a drain terminal, a gate terminal and a back gate terminal, where the source terminal is connected to the back gate terminal and forms the anode terminal of the active diode, and the drain terminal forms the cathode terminal of the active diode. The active diode further includes an offset bias voltage source having a first terminal and a second terminal; and an amplifier having a non-inverting input terminal and an inverting input terminal, and an output terminal, where the inverting input terminal is connected to the drain terminal of the transistor, the non-inverting input terminal is connected to the first terminal of the offset bias source, the output terminal is connected to the gate terminal of the transistor, and the second terminal of the offset bias source is connected to the source terminal of the transistor.

Abstract: The present invention provides an amplifier for amplifying a high-frequency signal and outputting an amplified signal. The amplifier includes: an amplification element which is a bipolar transistor or a field-effect transistor; and an inductor connected between a base and a collector or between a gate and a drain of the amplification element. The inductance of the inductor is chosen so that, within a predetermined frequency range, a parallel resonance occurs with a parasitic capacitor of the amplification element and an intrinsic capacitor of the amplification element, the intrinsic capacitor being a base-collector capacitance or a gate-drain capacitance.

Abstract: Provided is a temperature-compensated bias circuit for a power amplifier, in which a first resistor (Rref) connected to a reference voltage is connected to a base terminal of a third transistor (Q3) and an emitter terminal of the third transistor is connected to a first diode (D1).