Abstract: Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

Abstract: In an active hybrid transformer circuit connected to both transmit and receive sides, a current driver is connected to a transmission path circuit through a common connection point of a load resistor and a replica resistor while a replica driver is connected to the replica resistor of which another connection point is directly connected to the receive side. The replica driver may be formed by a DAC of a current output type. A current ratio of the replica driver and the current driver is selected at a predetermined value so as to prevent a transmit signal from leaking into the receive side.

Abstract: This invention provides an electronic control unit is capable of suppressing electromagnetic noise having a frequency band used in a portable wireless apparatus, and capable of exhibiting a noise resistance property against electromagnetic noise. The electronic control unit including a constant voltage power supply circuit portion, an analog signal inputting circuit portion, and a conversion processing circuit portion, an analog sensor and a driving power supply being connected to the outside, and the unit being connected to the analog sensor through a power supply line and a signal line, in which the analog signal inputting circuit portion includes a current limiting circuit portion, an integrating circuit portion, a current limiting resistor, a signal noise absorbing circuit, and a first bypass capacitor, and capacitance (C1) and parasitic inductance (L1) of the first bypass capacitor are set in a range of 7×106<1/[2??(L1×C1)]<35×106.

Abstract: Embodiments of the present invention relate to a circuit that varies the delay time of a clock signal in response to a frequency of the clock signal. The circuit may include a sensor and a delay circuit. The sensor may output a determination of the frequency of the clock signal. The delay time of the delay circuit may be responsive to the determination of a frequency of the clock signal. Accordingly, when the frequency of a clock signal varies, a delay of that clock signal can be varied to accommodate for the change in frequency.

Abstract: A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

Abstract: A sampling switch is the one for sampling an input voltage and providing an output voltage, comprising a MOS transistor for being supplied by the input voltage to the source terminal thereof and providing the output voltage from the drain terminal thereof; and a gate voltage control unit for supplying a voltage to the gate terminal of the MOS transistor with a delayed time from the input voltage. This enables a change in the on-resistance of a MOS transistor used for a sampling switch to be suppressed to a minimum, thereby reducing a distortion of signals induced by a change in the on-resistance.

Abstract: A triangular wave generating circuit adapted to a class-D amplifier is designed not to use a PLL circuit and to secure robustness regarding an amplification gain irrespective of variations of voltages, thus producing a high-quality triangular wave with a simple circuit constitution. First and second constant currents, which are generated in proportion to positive and negative voltages, are alternately and periodically selected using high impedance elements without causing noise. A first integrator produces a triangular wave in response to charged electricity realized by the first and second constant currents, wherein the triangular wave is supplied to a second integrator performing servo-amplification operation so as to suppress phase shifts thereof. Hence, it is possible to maintain a constant gain for the class-D amplifier irrespective of variations of voltages since the maximal and minimal voltages values of the triangular wave are made proportional to the positive and negative voltages.

Abstract: A charge pump circuit with resistively attenuated inputs is described herein. By reducing a voltage swing of input signals supplied thereto, the charge pump circuit described herein is configured for producing output signals with relatively low static phase offset even when operating at relatively low power supply voltages (e.g., less than about 1.2 volts). In general, the input voltage swing may be reduced by coupling an attenuator to each input of the charge pump circuit. A method for operating the differential charge pump is described, along with exemplary devices (e.g., PLL and DLL devices) within which the charge pump may be utilized.

Abstract: A method of driving a semiconductor switching element includes applying a drive signal configured to switch the semiconductor element such that a change in the charge stored on the drive electrode occurs over time, the drive signal having one or more predetermined parameters that define a time profile of the drive signal. The method also includes determining a deviation between an ideal switching instant of the semiconductor switching element and an actual switching instant of the semiconductor switching element, the ideal switching instant defined in reference to the time profile of the drive signal and/or a signal having a characteristic that is dependent on the time profile of the drive signal. The method further includes changing at least one of the predetermined parameters of the drive signal for a next switching operation based on the determined deviation.

Abstract: A method and apparatus are provided for summing DC voltages, which employ at least one native transistor device to add a first DC input voltage to a second DC input voltage to produce a sum output.

Abstract: Long existing performance, noise, and power consumption problems of prior art output drivers are solved by using n-channel transistors as pull up transistors and p-channel transistors as pull down transistors for high performance output drivers. Output drivers of the present invention can be fully compatible with HSTL or SSTL interfaces without using termination resistors. High resolution switching applications are also made possible without consuming much power. Output drivers of the present invention provide excellent solutions to support high performance interface while consuming much lower power.

Abstract: A power driver circuit is provided including a low voltage source, a high voltage source, at least one input signal line, an output node, and circuitry adapted to connect the output node to the low voltage source when the input signal line is in a first state and to the high voltage source when said input signal line is in a second state.

Abstract: A constant voltage outputting apparatus includes a differential amplifier circuit, an amplifier circuit, a current adjustment device and a stabilization circuit. The differential amplifier circuit performs a differential amplifying operation and outputs a differential amplified voltage. The amplifier circuit amplifies the differential amplified voltage output from the differential amplifier circuit. The current adjustment device adjusts a current characteristic of the amplifier circuit. The stabilization circuit stabilizes a state of the current adjustment device. A constant voltage outputting method is also described.

Abstract: A circuit comprising an active pull-up device coupled to a level shift circuit is coupled to a one-wire bus to allow communication devices coupled to the bus to better detect digital communication signals propagating through the bus. The level shift circuit provides a reference voltage signal that is typically above the circuit ground. Communication devices coupled to the bus are better able to detect digital communication signals propagating through the bus because such signals are raised above at least a portion of the noise signals on the bus.

Abstract: A variable capacitance charge pump system has a charge pump circuit with a variable capacitance. A pump clock driver circuit has a clock signal and is coupled to an input of the charge pump circuit. A feedback system has an enable signal coupled to an input of the pump clock driver circuit.

Abstract: A silicon-on-insulator (SOI) sense amplifier for sensing bit values stored in a memory cell, includes first and second input field effect transistors (FETs), connected to first and second cross-coupled CMOS inverter FET pairs. The input FETs are implemented as floating body FETs, which decreases gate capacitances and increases sense operation speed. History effect problems are minimized as threshold voltage differences are kept small.

Abstract: A low voltage bandgap reference circuit based on a current summation technique where reference voltages with positive and negative temperature coefficients are generated by a first circuit. These reference voltages are coupled to amplifying circuits which generate reference voltages with equal and opposite temperature coefficients based on the ratio of resistors in these amplifying circuits, thereby producing a temperature independent reference voltage. The current from each of these amplifying circuits is then summed in a summing resistor, where the size of the resistor determines the magnitude of the temperature independent reference voltage.

Abstract: A Schmitt trigger includes a PMOS transistor and an NMOS transistor, each having a gate coupled to an output voltage terminal. The Schmitt trigger is configured such that an input voltage that switches on the PMOS transistor determines a low voltage threshold and an input voltage that switches on the NMOS transistor determines a high voltage threshold. By coupling devices such as diodes to either or both of the PMOS and NMOS transistors, a margin between the low voltage threshold and ground and between the high voltage threshold and a supply voltage are maintained as the supply voltage is reduced. In addition, hysteresis is maintained or increased as supply voltage is increased.

Abstract: A feedback control system and method thereof are provided. The feedback control method includes (a) comparing the level of a reference signal with the levels of first and second signals, (b) if the levels of the first and second signals are lower than the level of the reference signal, generating a first control signal, if the levels of the first and second signals are higher than the level of the reference signal, generating a second control signal, and if the level of the reference signal is between the level of the first signal and the level of the second signal, generating a third control signal, (c) controlling the level of an output signal in response to the first through third control signals, and (d) outputting the controlled output signal and generating the first signal and the second signal.

Abstract: Data storage circuits and components of such circuits constructed using nanotube switching elements. The storage circuits may be stand-alone devices or cells incorporated into other devices or circuits. The data storage circuits include or can be used in latches, master-slave flip-flops, digital logic circuits, memory devices and other circuits. In one aspect of the invention, a master-slave flip-flop is constructed using one or more nanotube switching element-based storage devices. The master storage element or the slave storage element or both may be constructed using nanotube switching elements, for example, using two nanotube switching element-based inverters. The storage elements may be volatile or non-volatile. An equilibration device is provided for protecting the stored data from fluctuations on the inputs. Input buffers and output buffers for data storage circuits of the invention may also be constructed using nanotube switching elements.