Abstract: Circuitry is disclosed for controlling the slope of rising and falling edges of a signal. The circuitry includes a ramp signal generator that receives an input signal and that generates a trapezoidal signal based on the input signal, and a circuit array that receives the trapezoidal signal and that generates control signals based on the trapezoidal signal. Output transistors have gates that receive a set of the control signals. The output transistors include a top transistor and a bottom transistor. The top transistor has a source connected to a supply potential and a drain connected to an output. The bottom transistor has a source connected to a reference potential and a drain connected to the output. The top transistor and the bottom transistor are gated by the control signals to control a shape of an edge of an output signal at the output.

Abstract: A single-stage clock booster produces a boosted clock voltage on an output node that is a multiple of a supply voltage. The single-stage clock booster includes a pump capacitor having a first terminal being driven by a first control phase signal. A first switch is controlled by the boosted clock voltage for connecting a second terminal of the pump capacitor to the supply voltage during a charge phase. A second switch connects the second terminal of the pump capacitor to the output node during a boosted clock voltage output phase. A switching circuit alternately connects a control node of the second switch to the supply voltage and to the first terminal of the pump capacitor. The switching circuit is driven by a second control phase signal. A third switch is controlled by a third control phase signal for connecting the output node to a reference voltage during the charge phase.

Abstract: A DC symmetrical FET switch includes second and third switches connecting the well of the symmetrical FET switch to the drains and the source when the symmetrical FET switch is on. When the three FET's are on, the well, source and drain of the symmetric FET switch all exhibit the same input signal, wherein the drains and source to well capacitances are substantially prevented from draining off any of the input signal, thereby increasing the bandwidth and decreasing the insertion loss of the switch. The second and third switches are also FET switches. An enable signal is connected to the gates of all three FET's turning them on and off together. When the enable is false the FET switches are turned off and their wells are driven to a potential a proper potential. When the FET's are n-type the potential is low and when the FET's are p-types the potential is high.

Abstract: Method and apparatus for an ultra-drowsy circuit for use in lower power operational modes are described.

Abstract: In an operation to supply an input signal IN having an amplitude equal to a first power-supply voltage VDD1 to the gate of a PMOS transistor PM51 operating at a second power-supply voltage VDD2 higher than the first power-supply voltage VDD1, the levels of signals are converted by using PMOS transistors PM1 to PM4. A signal obtained as a result of the conversion is output from the PMOS transistors PM1 and PM2, being used for controlling electrical conduction of a PMOS transistor PM51.

Abstract: A sample and hold circuit including a first arrangement for receiving an input signal; a second arrangement for sampling and holding the signal in response to a control signal; and a third arrangement for minimizing the change in an input transistor's base current when the circuit switches from track to hold or hold to track and for keeping the collector emitter voltage constant at the input transistor. An arrangement is disclosed to increase the dynamic current accuracy of a current mirror for a diode connected transistor, by holding the voltage across one transistor in the current mirror constant. Another arrangement is disclosed for holding collector to emitter voltage constant for intermediate transistors resulting in improved gain accuracy and linearity. In one embodiment, a dummy leg is added to isolate the output voltage from switching transients that occur when an intermediate transistor is turned on at the transition from track to hold.

Abstract: A sample and hold circuit including a sampling capacitor for storing a sample of an input signal, an output stage for outputting the sample stored on the sampling capacitor; and input circuitry for sampling the input signal and storing the sample on the sampling capacitor. The input circuitry includes an autozeroing input buffer which selectively samples the input signal during a first operating phase and holds a sample of the input signal during a second operating phase. The autozeroing input buffer cancels any offset error. The input circuitry also includes switching circuitry for selectively coupling the sampling capacitor with an input of the sample and hold circuitry during the second operating phase and to an output of the autozeroing input buffer during the first operating phase.

Abstract: A comparator includes a circuit which provides a plurality of common-mode difference signals in response to differential input signals. The circuit provides a common-mode feedback signal in response to the plurality of common-mode difference signals. The common-mode feedback signal is used to drive the common-mode level of an amplifier to a desired value.

Abstract: A sense amplifier for a content addressable memory (CAM) device can utilize charge sharing between a match line and a pseudo-supply line to indicate a mis-match indication. A sense amplifier (200) can include match line (202) that can be precharged to a high supply potential (VCC), a sense node (206), and a pseudo-VSS (PVSS) line (204) that can be precharged to a low supply potential (VSS). In a match result, match line (202) can remain precharged, keeping sense device (P2) turned off, and sense node (206) remains low, generating a low output signal (SAOUT). In a mis-match result, match line (202) and sense node (206) can be equalized. A resulting drop in match line (202) potential can turn on sense device (P2), and sense node (206) can be pulled high. As a result, output signal (SAOUT) can be driven high.

Abstract: A temperature-sensing circuit includes a first circuit block outputting an output voltage having negative or positive temperature coefficients and a second circuit block amplifying the output voltage of the first circuit block to a predetermined amplitude and outputting the amplified output voltage. It further includes a third circuit block producing a voltage having temperature coefficients of a polarity opposite to that of the first circuit block and adding the produced voltage to the output voltage of the second circuit block to cancel out components of second order temperature coefficients contained in the output voltages of the first and second circuit blocks.

Abstract: A temperature sensing circuit and method are provided. An example temperature sensing circuit includes a temperature sensing unit that outputs a temperature signal indicating whether the temperature in the semiconductor device is higher or lower than a reference temperature in response to a first current control signal or a second current control signal by using a first current level that is increased when the temperature rises and a second current level that is reduced when the temperature rises. The temperature sensing unit also includes a storage unit that stores and outputs the temperature signal, and a controller that changes the first current level or the second current level in response to the temperature signal output from the storage unit and generates the first current control signal or the second current control signal used to control the reference temperature.

Abstract: A resampler filter for use in an analog phase-locked loop has a charge pump and one or more switched capacitors switched by signals derived from a voltage controlled oscillator in the phase locked loop.

Abstract: Comparison circuits are provided, corresponding to a plurality of pull up transistors, each for comparing a voltage at an output node and each respective reference voltage different in voltage level from other, and for adjusting a drive current of a corresponding output pull up transistor, and further comparison circuits are provided, corresponding to a plurality of pull down transistors, each for comparing the voltage of the output node and each respective reference voltage different in voltage level from other, and each for adjusting an amount of a drive current of a corresponding pull down transistor in accordance with a result of comparison. The reference voltages each are set to a voltage level between a power supply voltage and a ground voltage. Without a dedicated power supply pin terminal, a signal of a small amplitude having the amplitude limited stably and precisely can be output at high speed.

Abstract: An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.

Abstract: A gate driving circuit according to the present invention having, an output circuit which is connected to a first power supply terminal and a ground terminal and, upon receiving an ON/OFF signal, changes a level of a gate output terminal between a power supply voltage and a ground voltage, a shunt switching element which is connected between the gate output terminal and the ground terminal and is ON/OFF-controlled upon receiving a shunt control signal, and an output shunt control circuit which monitors the level of the gate output terminal and outputs the shunt control signal, wherein when the level of the gate output terminal decreases to not more than a first threshold value, the output shunt control circuit turns on the shunt switching element, and while the level is not more than a second threshold value larger than the first threshold value, the output shunt control circuit supplies the shunt control signal to said shunt switching element to maintain an ON state of the shunt switching element.

Abstract: The invention refers to a circuit device (1) with at least one connection (3b), to which a clock pulse (/CLK, /CLKT) can be applied, whereby the circuit device (1) also comprises a clock pulse detection facility (2) for detecting whether there is a clock pulse (/CLK, /CLKT) present at the connection (3b), or whether there is no clock pulse (/CLK, /CLKT) present at the connection (3b).

Abstract: A circuit making use of a push/pull-type control chip to drive a half-bridge inverter of dual N-MOS connects a drive circuit to a conventional half-bridge inverter circuit, and has a push/pull-type control chip having two output terminals, a drive circuit having two input terminals and two output terminals, and a half-bridge switch assembly having a first N-MOS FET and a second N-MOS FET. The two input terminals of the drive circuit are connected with the two output terminals of the push/pull control chip and controlled by the push/pull-type control chip. Each of the two N-MOS FETs of the half-bridge switch assembly has a control terminal, which is connected to one of the two output terminals of the drive circuit and driven by the drive circuit for converting a DC power source into an AC power source sent to the primary side of a transformer.

Abstract: A buffer circuit includes a differential amplifier, a buffering inverter, and a reference voltage monitoring circuit. The differential amplifier has a reference voltage and a current source as inputs. The buffering inverter has an output of the differential amplifier as an input. The reference voltage monitoring circuit includes two transistors and a second current source. An output of the reference voltage monitoring circuit is connected to the buffering inverter so as to minimize an effect of a variation in the value of the reference voltage on signal propagation delay times. The buffer circuit can further include a driver circuit with a comparator. A method of managing signal propagation delays includes providing a differential amplifier, providing at least one buffering inverter, and providing a reference voltage monitoring circuit. The reference voltage monitoring circuit can maintain signal propagation delays as a reference voltage varies.

Abstract: A system for driving a differential signal on a signal line and converting the differential signal from a rail-to-rail differential signal to a small signal differential signal is described. An exemplary embodiment of the circuit includes a first programmable differential driver circuit receiving a differential input; a programmable delay circuit receiving the differential input and coupled to a second programmable differential driver circuit; and a summation circuit coupled to the first and second differential driver circuits.

Abstract: Methods for obtaining a sampling phase to generate image information according to an analog image signal and timing information are performed. In an exemplary method, sampling clocks having a predetermined phase difference therebetween is sequentially generated according to timing information. The analog image signal is sampled using the sampling clocks, and sequential sampled values corresponding to each sampling clock are generated. The sampled values are detected to obtain edges formed by the sampled values. Magnitudes of the edges are accumulated to generate accumulation values. An optimum sampling clock is obtained according to the accumulation values. The optimum sampling clock corresponding to the accumulation value is the largest one among the accumulation values corresponding to the adjacent sampling clocks, and the difference among the accumulation values corresponding to the adjacent sampling clocks is within a predetermined range.