Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

Abstract: Described herein is a semiconductor structure and method of manufacture. The semiconductor structure includes a plurality of semiconductor fins on a substrate and a plurality of raised active regions, wherein each raised active region is located on sidewalls of a corresponding semiconductor fin among said plurality of semiconductor fins. The raised active regions are laterally spaced from any other of the raised active regions. Each raised active region comprises angled sidewall surfaces that are not parallel or perpendicular to a topmost horizontal surface of said substrate. The raised active regions are silicon germanium (SiGe). The semiconductor structure includes a metal semiconductor alloy region contacting at least said angled sidewall surfaces of at least two adjacent raised active regions. The semiconductor alloy region includes a material selected from the group consisting of nickel silicide, nickel-platinum silicide and cobalt silicide.

Abstract: An optoelectronic apparatus is provided, comprising a carrier device that has a longitudinal extent and a transverse extent, wherein the carrier device has a plurality of electrically conductive tracks aligned in parallel with the longitudinal extent, and wherein the carrier device has a plurality of contact chambers aligned in parallel with the transverse extent at an upper side. Each of the contact tracks is electrically contactable in each contact chamber to be able to install at least one optoelectronic transmitter and/or at least one optoelectronic receiver in a variable mounting in the respective chamber.

Abstract: In a semiconductor device including a crystalline nitride layer, in which diamond is used for heat dissipation thereof, it is an object of the present invention to suppress cracking of the crystalline nitride layer. The semiconductor device includes a layered body and a heat dissipation layer. The layered body includes a crystalline nitride layer and a composite layer. The composite layer includes a non-inhibiting portion which does not inhibit diamond growth on a surface thereof and an inhibiting portion which inhibits the diamond growth on the surface. A layered body main surface of the layered body has a first region in which the non-inhibiting portion is exposed and a second region in which the inhibiting portion is exposed. The heat dissipation layer is made of diamond, opposed to the main surface, adhered to the first region, and separated from the second region with a void interposed therebetween.

Abstract: Disclosed is a semiconductor device including a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction, a first gate structure that extends across the first and second active patterns, a second gate structure that is spaced apart from the first gate structure, and a node contact between the first and second gate structures that electrically connects the first active pattern and the second active pattern to each other. The node contact comprises a first end adjacent to the first active pattern and a second end adjacent to the second active pattern. The second end of the node contact being shifted in the first direction relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.

Abstract: To improve a degree of design freedom of a display surface of a device while maintaining a reliability of the device, provided is a display device including an active region that contributes to a display, and a notch formed in a position surrounded by an end portion of the active region. A protruding portion is formed on a peripheral end side of the active region where the notch is formed. A light-emitting layer is disconnected as a result of a step at the protruding portion.

Abstract: A three-dimensional (3D) stack is provided and includes a capacitor layer and an integrated circuit (IC) layer. The capacitor layer includes capacitors and capacitor layer connectors respectively communicative with corresponding capacitors. The IC layer is stacked vertically with the capacitor layer and is hybridized to a detector. The IC layer includes IC layer connectors respectively communicative with corresponding capacitor layer connectors.

Abstract: Provided is a light emitting device package including: a light emitting device; a light transmitting plate body formed above the light emitting device and including a lower light transmitting plate, a plurality of side light transmitting plates formed on an upper surface of the lower light transmitting plate, an upper light transmitting plate corresponding to the upper surface of the lower light transmitting plate and formed on upper surfaces of the plurality of side light transmitting plates, and an empty portion formed inside; a wavelength converting unit including a first wavelength converting layer formed on a lower surface of the lower light transmitting plate and a second wavelength converting layer formed in the empty portion and covering the upper surface of the lower light transmitting plate; and an adhesive layer formed between the first wavelength converting layer and the light emitting device, in which the adhesive layer is formed on at least one side and an upper surface of the light emitting dev

Abstract: A semiconductor device includes a substrate, a conductive pattern on the substrate, a lower electrode electrically connected to the conductive pattern, a dielectric layer covering a surface of the lower electrode, a first upper electrode on the dielectric layer, a diffusion barrier on an upper surface of the first upper electrode, and a second upper electrode covering the diffusion barrier, the second upper electrode including a different material from that of the first upper electrode.

Abstract: Thermal pattern sensor including a matrix of multiple rows and columns of pixels, each pixel comprising: - a pyroelectric capacitor comprising a pyroelectric portion positioned between lower and upper electrodes, in which a first of these electrodes forms a readout electrode; and —a heating element that is capable of heating the pyroelectric portion of said pixel; and in which: - for each row of pixels, the heating elements are capable of heating the pyroelectric portion of the pixels of the row independently of the heating elements of the pixels of the other rows; and —for each column of pixels, the readout electrodes of each pixel are electrically linked to one another and are formed by a first electrically conductive portion that makes contact with the pyroelectric portions of the pixels of the column, and that is separate from the first portions of the other columns.

Abstract: InGaN layers characterized by an in-plane lattice constant within a range from 3.19 to 3.50 ? are disclosed. The InGaN layers are grown by coalescing InGaN grown on a plurality of GaN regions. The InGaN layers can be used to fabricate optical and electronic devices for use in light sources for illumination and display applications.

Abstract: The present application relates to a technical field of semiconductors, and discloses a device having a physically unclonable function, a method for manufacturing same, and a chip using same.

Abstract: Provided is a layout configuration that helps facilitate manufacturing a semiconductor integrated circuit device including a nanowire FET. A nanowire FET in a standard cell includes Na (where Na is an integer of 2 or more) nanowires extending in an X direction, and a nanowire FET in a standard cell includes Nb (where Nb is an integer of 1 or more and less than Na) nanowires extending in the X direction. At least one of both ends, in the Y direction, of a pad of the nanowire FET is aligned in the X direction with an associated one of both ends, in the Y direction, of a pad of the nanowire FET.

Abstract: This invention provides a nitride semiconductor light emitting device in which current concentration is suppressed without excessively increasing resistance at a low cost without increasing a manufacturing process. The planar shape of a mesa portion configuring a nitride semiconductor light emitting device is a shape containing a convex-shaped tip portion 352b formed by a curved line or a plurality of straight lines and a base portion 352a continuous to the convex-shaped tip portion 352b, in which an obtuse angle is formed by adjacent two straight lines in the convex-shaped tip portion formed by the plurality of straight lines. The first electrode layer 4 has visible outlines 411 and 412 along a visible outline 302 of the mesa portion through a gap 9 in planar view. The relationship between a gap W1 in the convex-shaped tip portion 352b and a gap W2 in the base portion 352a is W1> W2.

Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

Abstract: Device structures and methods are provided for fabricating vertical field-effect transistor devices with non-uniform thickness bottom spacers to achieve increased device performance. For example, a semiconductor substrate surface is etched to form semiconductor fins having bottom portions with concave sidewall surfaces that undercut upper portions of the fins. A doped epitaxial source/drain layer is formed on the concave sidewall surfaces, wherein portions of the doped epitaxial source/drain layer disposed between the fins have a raised curved surface. A bottom spacer layer is formed on the doped epitaxial source/drain layer, wherein portions of the bottom spacer layer disposed between the fins have a curved-shaped profile with a non-uniform thickness.

Abstract: An organic light-emitting display apparatus including: a substrate; a plurality of pixels that are formed on the substrate and each have a light emission area from which visible rays are emitted and a transmission area through which external light is transmitted; a pixel circuit portion disposed in each light emission area of the plurality of pixels; a first electrode that is disposed in each light emission area and is electrically connected to the pixel circuit portion; an intermediate layer that is formed on the first electrode and includes an organic emissive layer; a second electrode formed on the intermediate layer; and a capping layer that is disposed on the second electrode and includes a first capping layer corresponding to the light emission area and a second capping layer corresponding to the transmission area. Accordingly, electrical characteristics and image quality of the organic light-emitting display apparatus may be improved.

Abstract: Provided herein is an apparatus including a cavity in a first side of a first silicon wafer, and an oxide layer on the first side and in the cavity. A first side of a second silicon wafer is bonded to the first side of the first silicon wafer. A gap control structure is on a second side of the second silicon wafer, and a MEMS structure in the second silicon wafer. A eutectic bond is bonding the second side of the second silicon wafer to a third silicon wafer. A lower cavity is between the second side of the silicon wafer and the third silicon wafer, wherein the gap control structure is outside of the lower cavity and the eutectic bond.

Abstract: A display device includes a substrate, a first pixel circuit, a second pixel circuit, a third pixel circuit, a protective layer, a first conductive structure, a second conductive structure, a third conductive structure, first light emitting diodes (LEDs), second LEDs and third LEDs. The first pixel circuit, the second pixel circuit and the third pixel circuit are located on the substrate. The second pixel circuit is located between the first pixel circuit and the third pixel circuit. The protective layer covers the first pixel circuit, the second pixel circuit and the third pixel circuit. The first conductive structure is electrically connected to the first pixel circuit through the first opening of the protective layer. The first LEDs are overlapped with the first pixel circuit and the second pixel circuit. The first LEDs are electrically connected to the first conductive structure.

Abstract: An electroluminescent display device includes a substrate, a bank for defining an emission area on the substrate, an emission layer in the emission area defined by the bank, an electrode on the emission layer and the bank, and a conductive layer on the electrode, wherein the electrode includes a first portion having a relatively small thickness, and a second portion having a relatively large thickness, and the conductive layer is in contact with the first portion of the electrode, and wherein the conductive layer is provided on the electrode, and more particularly, the conductive layer is provided in such a way the conductive layer is in contact with the relatively-thin first portion of the electrode so that it is possible to prevent problems related with a burning phenomenon or wiring disconnection in the first portion of the electrode.