Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads, and a plurality of wire contacts; a plurality of leads; a plurality or wires, and a resin molded over the majority of the package. The leads have substrate connecting portions and wire connecting portions. A first side of the substrate connecting portions of the leads connects to the bonding pads on the semiconductor chip. Second sides of the substrate connecting portions of the leads are exposed, i.e., they are not covered with the molding resin. The wires are connected between the wire connecting portions of the leads and the wire contacts on the semiconductor chip. The wire connecting portion of at least one of the leads may be split into at least two branches. In addition, grooves may be formed on the exposed portions of the substrate connecting portions of the leads so that the grooves are engageable with corresponding projections on a device upon which the semiconductor package will be mounted.

Abstract: A die seal structure for a small-dimension semiconductor integrated circuit is disclosed. The die seal structure, which lies between an integrated circuit region and a scribe line over a semiconductor wafer, includes at least one dielectric layer over the semiconductor wafer. At least one contact window is formed in the dielectric layer. The die seal structure further includes at least one plug each filled in one of the contact windows.

Abstract: An additional high quality insulating layer is grown over the substrate after the formation of the gate electrode of a thin film transistor (TFT). The growth temperature of the insulating layer can be higher than conventional method and the insulating layer is more free of pin-holes. After the insulating layer in the thin oxide region of the TFT is etched away, conventional fabrication processes are followed. The dielectric of the thin film oxide region is the same as that of the conventional TFT; but the dielectric in the vicinity of the thin oxide region, the crossovers of the data lines and the scan lines, and the gate dielectric layer of the TFT are now composed of the high quality insulating layer. The TFT structure can improve the yield of fabrication by confining the channel region in the shadow of the gate electrode to reduce the leakage photo-current, and by reducing the steps at cross-overs steps and interconnections to avoid open-circuit.

Abstract: A semiconductor device comprising first and second interconnect levels (14) and (16) is described. Mixed polymeric intermetal dielectrics (46), (48) and (50) are used to separate conductive elements (22), (24), (26), (36) and (38), respectively. The intermetal dielectric bodies (46), (48) and (50) comprise a mixture of perfluorinated and non-fluorinated parylene.

Abstract: A semiconductor device which can interconnect different types of impurity region without increasing a contact resistance including a first impurity diffusion region formed on a first portion of a semiconductor substrate, a second impurity diffusion region formed on a second portion of the semiconductor substrate, an interlevel insulating layer having a contact hole exposing the first and second impurity regions on the semiconductor substrate, a first conductive layer formed on the interlevel insulating layer, a second conductive layer formed on the overall surface of the substrate, wherein the second conductive layer formed on the first impurity diffusion region is doped with the same impurities as doped into the first impurity diffusion region and the second conductive layer formed on the second impurity diffusion region is doped with the same impurities as doped into the second impurity diffusion region, and a manufacturing method thereof are disclosed.

Abstract: A TFT circuit according to the present invention includes a first transistor and a second transistor both formed on an insulating substrate. The first transistor has a channel region comprising a polycrystalline silicon film to which a metal element for enhancing crystallization is added. The second transistor has a channel region comprising a polycrystalline silicon film to which no metal element for enhancing crystallization is added.

Abstract: A light emitting device with higher luminance than that of a conventional light emitting device is provided.

Abstract: A semiconductor device includes a substrate having a first surface, a second surface and at least one conductor parts which are exposed at both the first and second surfaces of the substrate, a semiconductor chip provided on the first surface of the substrate and having a plurality of electrode pads, a plurality of leads, a plurality of bonding-wires electrically connecting the leads and the conductor parts to corresponding ones of the electrode ads of the semiconductor chip, and a resin package encapsulating the semiconductor chip, part of the leads, and the substrate so that the conductor parts are exposed at the second surface of the substrate.

Abstract: A lead-frame for a semiconductor device has an input lead partially projecting from both sides of the semiconductor device and an output lead projecting from both sides of the semiconductor device and connected through bonding wires to bonding pads on a semiconductor chip, and one end portion of the input lead and one end portion of the output lead both unused for an electrical connection to a circuit board are separated from the remaining portions so as to decrease a parasitic capacitance.

Abstract: A package assembly (31) has a leadframe (10) including a locating flange (30), an optical transmitter (22) such as a laser diode mounted to the leadframe, and a package (32) enclosing both the optical transmitter and a portion of the leadframe so that the locating flange of the leadframe is disposed outside of the package. The locating flange is used as a reference datum to align the optical transmitter's relative height and lateral position during manufacture. Also, the locating flange is used as a reference datum in mating the package assembly to other, standard optical components when mounting to other components in an optical end product.

Abstract: An auxiliary MOSFET is integrated into a lateral IGBT structure with the source and drain of the auxiliary MOSFET in parallel with the emitter-base circuit of the IGBT. A driver, integrated with the IGBT chip, turns off the base emitter voltage to the IGBT before turning off the auxiliary MOSFET during turn off. The auxiliary MOSFET is turned off again at the beginning of the conduction period to ensure full conductivity modulation of the DMOS drain and maximum gain of the PNP transistor. Short circuit protection and overtemperature protection circuits are also integrated into the chip.

Abstract: The present invention relates to a window clamp and a method of alignment of lead frame strip utilizing the same and, more particularly, to a window clamp and method of alignment of lead frame strip utilizing the same which makes the alignment of the lead frame strip precise, fast and increases yield by sensing an alignment condition of a die and a lead frame by utilizing a window clamp formed with a bonding window and a lead sensing window and by utilizing a sensing means set on a wire bonding equipment to prevent the occurrence of poor quality at the time of wire bonding due to misalignment of the lead frame strip.

Abstract: An integrated circuit includes a substrate with doped regions, a patterned polysilicon layer defining contacts and local interconnects, a submetal dielectric, a two-metal layer metal interconnect structure with an intermetal dielectric layer, and a passivation layer. Like the dielectric layers, the passivation layer is optically transparent, thick, and planarized. Because of this, laser energy can be directed through the passivation layer to fuse two conductors of the top metal layer without delaminating the passivation layer. In addition, laser energy is directed through the passivation layer and the intermetal dielectric to fuse pairs of conductors in the lower metal layer. Thus, the present invention provides for reliable convenient circuit modification without disturbing dielectric and exposing metal features to moisture and other contaminants.

Abstract: A central portion of a front surface of a first semiconductor chip is bonded to a first surface of a die pad of a lead frame via an elastic insulating film. A peripheral portion having electrodes of the front surface is outside of the die pad. With a back surface of the first semiconductor chip put in contact with a jig surface, wire bonding of the first semiconductor chip is performed. Then, with a second surface of the die pad opposite from the first semiconductor chip put in contact with a jig surface, a back surface of a second semiconductor chip is bonded to the back surface of the semiconductor chip via an adhesive. With the second surface of the die pad put in contact with a jig surface, wire bonding of the second semiconductor chip is performed.

Abstract: A multiple-chip IC package used to contain a number of chips therein is provided. The multiple-chip IC package includes a leadframe, at least one IC chip mounted on the leadframe, and at least one dummy chip mounted on a second area on the leadframe. On the dummy chip, there is provided with a plurality of bonding pads which serve as intermediate bonding pads between the chips and the pins on the leadframe so that any two connecting points are connected by a number of straight wires via the dummy chip. This allows the wire bonding process to be much easier to conduct. Further, the method for assembling this multiple-chip IC package includes a first step of mounting the chips on a leadframe; a second step of mounting at least one dummy chip having a plurality of bonding pads thereon on a selected area on the leadframe; and a third step of conducting a wire bonding process to interconnect between the chips and the pins.

Abstract: A plurality of JFETs (junction field-effect transistors) can be formed on the same substrate while being electrically separated from each other, and can be also combined with a CMOS (complementary metal-oxide semiconductor). A P.sup.- type Si layer 14 is fabricated on a semiconductor substrate 11 as an island. On this island of P.sup.- type Si layer, an N.sup.+ source region 19 and N.sup.+ drain region, and a channel region having a length of "Lg" and a channel depth of "Tg" are fabricated. The shape of the gate region with the gate length of "Lg" is not a V-shaped-structure. Another P type layer 21 of the gate region is fabricated on the same plane as the source region 19 and the drain region 15.

Abstract: A lateral transistor includes a first conductivity type semiconductor substrate, a first second conductivity type region in the substrate, a second second conductivity type region in the substrate spaced from and partially surrounding the first region including a plurality of sides and corners; an electrically insulating film covering the semiconductor substrate and including respective penetrating holes extending to the first and second regions; a first metal film disposed on the insulating film and contacting the second region through a first of the penetrating holes; and a second metal film disposed on the insulating film and contacting the first region through a second of the penetrating holes wherein the first metal film is missing opposite a first of the corners of the second region and the second metal film extends across the second region at the first corner.

Abstract: One embodiment of a metal oxide semiconductor controlled thyristor in accordance with the present invention has a semiconductor wafer with opposing first and second surfaces. The wafer includes first through sixth sequential regions which are disposed one above the other. The first region includes the second surface of the wafer and each of the second through sixth regions has at least a portion which extends up to the first surface. The first, third, and sixth regions have a first type of conductivity and the second, fourth, and fifth regions have a second type of conductivity. A trench with a bottom and sidewalls extends from the first surface and passes through the fourth, fifth, and sixth regions and into the third region. A dielectric material coats the bottom and sidewalls of the trench and a conductive material fills the remainder of the trench.

Abstract: An integrated structure active clamp for the protection of a power device against overvoltages includes a plurality of serially connected diodes, each having a first and a second electrode, obtained in a lightly doped epitaxial layer of a first conductivity type in which the power device is also obtained; a first diode of said plurality of diodes has the first electrode connected to a gate layer of the power device and the second electrode connected to the second electrode of at least one second diode of the plurality whose first electrode is connected to a drain region of the power device; said first diode has its first electrode comprising a heavily doped contact region of the first conductivity type included in a lightly doped epitaxial layer region of the first conductivity type which is isolated from said lightly doped epitaxial layer by a buried region of a second conductivity type and by a heavily doped annular region of the second conductivity type extending from a semiconductor top surface to said bu

Abstract: The present invention provides a digital vertical multi-valued logic device including a substrate defining a horizontal plane and a vertical direction normal to the horizontal plane, a substantially vertical conductive gate structure disposed above the substrate, source and drain regions, a channel region positioned between the source and drain region and adjacent to the gate structure, the channel region including at least a first and second tunnel barrier forming a quantum well structure. The quantum well acts to incorporate an artificial bandstructure into the present invention modifying device performance. By introducing quantum wells into the device structure, quantum-mechanically defined drain voltage levels are introduced in the MOS transistors at which no current flows, creating stable intermediate logic levels.