Abstract: To increase the yield of the separation process. To produce display devices formed through the separation process with higher mass productivity. A first layer is formed using a material including a resin or a resin precursor over a substrate. Then, first heat treatment is performed on the first layer, whereby a first resin layer including a residue of an oxydiphthalic acid is formed. Then, a layer to be separated is formed over the first resin layer. Then, the layer to be separated and the substrate are separated from each other. The first heat treatment is performed in an atmosphere containing oxygen.

Abstract: The present disclosure provides a display panel and a fabricating method thereof, and a display device. The fabricating method for the display panel includes forming a glass adhesive layer on a packaging region of a first substrate, forming an OLED device on a display region of the first substrate, and aligning the first substrate with a second substrate, and forming a sealing structure between the first substrate and the second substrate by irradiating the packaging region with laser. The fabricating method for the display panel according to an embodiment of the present disclosure avoids the occurrence of the phenomenon that the coated glass adhesive layer and the evaporated organic light emitting layer are offset during the subsequent packaging process, by fabricating the glass adhesive layer on the substrate for forming the OLED device, thereby the production efficiency of the overall packaging process is enhanced.

Abstract: An organic light emitting device includes: a substrate (200), and a first electrode layer (201), a second electrode layer (202), a color conversion layer (206), a first light emitting layer (203), and a second light emitting layer (204) that are stacked on the substrate (200), wherein the first light emitting layer (203) is disposed between the first electrode layer (201) and the second electrode layer (202), the first light emitting layer (203) emits the first emission light under electric excitation; the first electrode layer (201) is a transparent electrode layer, the first color conversion layer (206) is disposed at one side of the first electrode layer (201) away from the second electrode layer (202); the second light emitting layer (204) is disposed between the first light emitting layer (203) and the second electrode layer (202), the second light emitting layer (204) emits the second emission light under electric excitation; and a peak wavelength of the first emission light is larger than a peak wavele

Abstract: A method for manufacturing a display substrate, a display substrate and a display device are disclosed. The method includes: forming a thin-film transistor (TFT) array on a base substrate to form an array substrate; and forming a pixel define layer (PDL) on a non-pixel region of the array substrate by a patterning process. A photochromic material is uniformly distributed in the PDL; the PDL provided with the photochromic material can be converted from light-transmitting to light-shielding under action of light illumination; and the process that the PDL is converted from light-transmitting to light-shielding is irreversible.

Abstract: An integrated circuit with a metal thin film resistor with an overlying etch stop layer. A process for forming a metal thin film resistor in an integrated circuit with the addition of one lithography step.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a plurality of dummy gates on a substrate, a capping layer on each dummy gate, and a dielectric layer over the substrate, wherein the dielectric layer has a top surface above each dummy gate. The method also includes performing a first ion implantation process on the dielectric layer to form a first stop layer in the dielectric layer. A top surface of the first stop layer is above or coplanar with a top surface of each dummy gate. Further, the method includes performing a first planarization process on the capping layer and the dielectric layer to expose the top surface of each dummy gate. A removal rate of the first stop layer is smaller than a removal rate of the dielectric layer when performing the first planarization process.

Abstract: Aspects of the present disclosure include a method of forming a semiconductor interconnect structure and the interconnect structure. The method includes etching an opening in a first interconnect dielectric material. The method includes performing a nitridation process that converts the surfaces of the opening into nitride residues, and forms a nitrided interconnect dielectric material surface in the opening. The method includes depositing tantalum to create a tantalum layer on the nitrided interconnect dielectric surface region. The method includes depositing copper to fill the opening and planarizing the surface of the first dielectric material.

Abstract: In some examples, a transistor includes a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.

Abstract: According to one embodiment, a semiconductor device includes an underlying metal film and a metal film. The underlying metal film is a tantalum-aluminum film having an aluminum content of more than 50 atomic % and less than 85 atomic %, a tungsten-zirconium film having a zirconium content of less than 40 atomic %, a tungsten-titanium film having a titanium content of less than 80 atomic %, or a tungsten film. The metal film is provided on the underlying metal film and in contact with the underlying metal film. The metal film contains at least one of tungsten and molybdenum, and has a main orientation of (100) or (111).

Abstract: A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.

Abstract: A structure includes an SRAM cell includes a first and a second pull-up MOS device, and a first and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. A first metal layer is over the gate electrodes of the MOS devices in the SRAM cell. The structure further includes a first metal layer, and a CVss landing pad, wherein the CVss landing pad has a portion in the SRAM cell. The CVss landing pas is in a second metal layer over the first metal layer. A word-line is in the second metal layer. A CVss line is in a third metal layer over the second metal layer. The CVss line is electrically coupled to the CVss landing pad.

Abstract: Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM).

Abstract: An embodiment of a method for metal-assisted chemical etching of a semiconductive substrate comprises forming a patterned coating on a top surface of a substrate layer of a silicon wafer; applying a noble metal layer over the patterned coating such that a portion of the noble metal layer is in contact with the top surface of the substrate layer; and immersing the silicon wafer in a wet etching solution to form a trench under the portion of the noble metal layer that is contact with the top surface of the substrate layer. Further, the trench may be filled with copper material to form a through silicon via structure. Such embodiments provide etching techniques that enable etched formations that are deep (e.g., high-aspect-ratio) and uniform as opposed to shallow etchings (i.e., low-aspect-ratio) or non-uniform deep etchings.

Abstract: In a method according to embodiments of the invention, a light emitting structure comprising a plurality of light emitting diodes (LEDs) is provided. Each LED includes a p-contact and n-contact. A first mount and a second mount are provided. Each mount includes anode pads and cathode pads. The anode pads are aligned with the p-contacts and the cathode pads are aligned with the n-contacts. The method further includes mounting the light emitting structure on one of the first and second mounts. An electrical connection on the first mount between the plurality of LEDs differs from an electrical connection on the second mount between the plurality of LEDs. The first mount is operated at a different voltage than the second mount.

Abstract: A manufacturing substrate, on which a lamination is formed, is disposed on a first substrate. The lamination includes a first sheet substrate having flexibility and adhered to the first substrate, an organic layer that emits light such that brightness is controlled in each of a plurality of pixels forming an image in a display area, and a sealing layer. A light blocking area that does not overlap the display area in a plan view is formed on the first substrate, and after the first substrate is irradiated with light on a side that opposite to the sheet substrate, the first substrate is delaminated from the first sheet substrate.

Abstract: The invention relates to a field-effect transistor and a method for its manufacturing having at least one layer, said layer comprising a III-V compound semiconductor, wherein the compound semiconductor comprises at least one element from the chemical group III being selected from any of gallium, aluminum, indium and/or boron and wherein the compound semiconductor comprises at least one element from the chemical group V being selected from nitrogen, phosphorous and/or arsenic, wherein the compound semiconductor comprises at least nitrogen, wherein the field-effect transistor comprises at least any of a source electrode and/or a drain electrode, said source electrode and/or drain electrode comprising at least one doped region extending from the surface into the at least one layer, wherein the depth of penetration of said doped region is selected from approximately 10 nm to approximately 200 nm.

Abstract: An organic light-emitting display device includes: a substrate; a pixel disposed on the substrate and including a first region that displays an image and a second region that transmits external light; a pixel circuit portion disposed in the first region and including at least one thin film transistor and at least one capacitor; a first electrode disposed in the first region and electrically connected with the pixel circuit portion; a pixel-defining layer including a first opening that exposes a portion of the first electrode and a second opening that corresponds to the second region; a second electrode facing the first electrode; an organic emission layer disposed between the first electrode and the second electrode; and a transparent wiring electrically connected with the pixel circuit portion and overlapping the second opening in a plan view.

Abstract: Embodiments of the present invention provide a compound optical filter device comprising a semiconductor substrate having an optical transducer formed on the semiconductor substrate, the optical transducer responsive to light to produce a signal or responsive to a signal to emit light. An optical filter comprises a filter substrate separate and independent from the semiconductor substrate and one or more optical filter layers disposed on the filter substrate. The filter substrate is micro-transfer printed on or over the semiconductor substrate or on layers formed over the semiconductor substrate and over the optical transducer to optically filter the light to which the optical transducer is responsive or to optically filter the light emitted by the optical transducer. In further embodiments, the optical filter is an interference filter and the semiconductor substrate includes active components that can control or operate the optical transducer.

Abstract: Packaged semiconductor die and CTE-engineering die pairs and methods to form packaged semiconductor die and CTE-engineering die pairs are described. For example, a semiconductor package includes a substrate. A semiconductor die is embedded in the substrate and has a surface area. A CTE-engineering die is embedded in the substrate and coupled to the semiconductor die. The CTE-engineering die has a surface area the same and in alignment with the surface area of the semiconductor die.

Abstract: An organic light emitting display device includes: a substrate including a display area having a plurality of pixel regions and a non-display area; a first electrode on the substrate; a first organic emissive layer on the first electrode; a charge generation layer on the first organic emissive layer as a common layer for the plurality of pixel regions; a second organic emissive layer on the charge generation layer; a second electrode on the second organic emissive layer as a common electrode for the plurality of pixel regions; and an anti-contact layer between the charge generation layer and the second electrode as a common layer for the plurality of pixel regions. The anti-contact layer completely surrounds the charge generation layer.