Abstract: Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess.

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

Abstract: Methods of forming a semiconductor structure include the use of channeled implants into silicon carbide crystals. Some methods include providing a silicon carbide layer having a crystallographic axis, heating the silicon carbide layer to a temperature of about 300° C. or more, implanting dopant ions into the heated silicon carbide layer at an implant angle between a direction of implantation and the crystallographic axis of less than about 2°, and annealing the silicon carbide layer at a time-temperature product of less than about 30,000° C.-hours to activate the implanted ions.

Abstract: Systems and methods are disclosed for manufacturing a CMOS-MEMS device. A partial protective layer is deposited on a top surface of a layered to cover a logic region. A first partial etch is performed from the bottom side of the layered structure to form a first gap below a MEMS membrane within a MEMS region of the layered structure. A second partial etch is performed from the top side of the layered structure to remove a portion of a sacrificial layer between the MEMS membrane and a MEMS backplate within the MEMS region. The second partial etch releases the MEMS membrane so that it can move in response to pressures. The deposited partial protective layer prevents the second partial etch from etching a portion of the sacrificial layer positioned within the logic region of the layered structure and also prevents the second partial etch from damaging the CMOS logic component.

Abstract: A semiconductor device of an embodiment includes a SiC layer having a surface, the surface inclined at an angle of 0° to 10° with respect to a {000-1} face or the surface having a normal line direction inclined at an angle of 80° to 90° with respect to a <000-1> direction, a gate electrode, a gate insulating layer provided between the surface and the gate electrode, and a region provided between the surface and the gate insulating layer, a maximum concentration of deuterium (D) in the region being 1×1020 cm?3 or more and a maximum concentration of hydrogen (H) in the region being 1×1019 cm?3 or less.

Abstract: The invention provides a light emitting device and a manufacturing method thereof, and a display device. The light emitting device comprises a base substrate and a laminated structure formed on the base substrate, the laminated structure including a first electrode, an organic layer and a second electrode which are laminated, the organic layer is provided between the first electrode and the second electrode, wherein the second electrode is provided with light extraction particles therein. In solutions of the light emitting device and the manufacturing method thereof, and the display device, the metal electrode is provided with light extraction particles therein, the light extraction particles destroy the surface plasma waves generated by the metal electrode, so that light fallen into the surface plasma waves can be extracted, the light extraction efficiency of the metal electrode is increased, and thus the light extraction efficiency of the light emitting device is increased.

Abstract: A diaphragm structure of a micromechanical component includes: a diaphragm integrated via at least one spring element into a layered structure, the diaphragm spanning a cavern, so that at least one section of the diaphragm edge extends up to and beyond the edge area of the cavern; and an anchoring structure formed in the overlap area between the diaphragm and the cavern edge area. The anchoring structure includes at least one anchor element structured out of the layered structure above the cavern edge area, and one through opening for the anchor element formed in the edge area of the diaphragm, so that there is a clearance between the anchor element and the through opening which allows for a mechanical stress relaxation of the diaphragm.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a substrate including a first region and a second region; buried gates formed in the first region and the second region, the buried gates in the second region having a different density distribution from the buried gates in the first region; first and second junction regions formed in the first and second regions, respectively, and having a same depth as each other; and a variable resistance element formed over the substrate and electrically connected to the buried gates in the first region. According to the implementations, the characteristics of the variable resistance element can be improved.

Abstract: A method for fabricating a test structure on a wafer includes forming a fin on a substrate, forming a first gate stack over the fin, the first gate stack having a first gate width, the first gate stack including a gate dielectric layer having a first thickness, forming a second gate stack over the fin, the second gate stack having a second gate width, the second gate stack including a gate dielectric layer having a second thickness, and forming a third gate stack over the fin, the third gate stack having a third gate width, the third gate stack including a gate dielectric layer having the second thickness, wherein the first gate stack is arranged a first distance from the second gate stack and the second gate stack is arranged the first distance from the third gate stack.

Abstract: Provided is a photodetector including a substrate, a first doped region on the substrate, a second doped region having a ring structure, wherein the second doped region is provided in the substrate, surrounds the first doped region and is horizontally spaced apart from a side of the first doped region, an optical absorption layer on the first doped region, a contact layer on the optical absorption layer, a first electrode on the contact layer, and a second electrode on the second doped region.

Abstract: A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.

Abstract: High-efficiency line-forming optical systems and methods for defect annealing and dopant activation are disclosed. The system includes a CO2-based line-forming system configured to form at a wafer surface a first line image having between 2000 W and 3000 W of optical power. The line image is scanned over the wafer surface to locally raise the temperature up to a defect anneal temperature. The system can include a visible-wavelength diode-based line-forming system that forms a second line image that can scan with the first line image to locally raise the wafer surface temperature from the defect anneal temperature to a spike anneal temperature. Use of the visible wavelength for the spike annealing reduces adverse pattern effects and improves temperature uniformity and thus annealing uniformity.

Abstract: A method for manufacturing a light-emitting device of the present invention includes a step in which solid-state sealing resin (17) containing a phosphor (18) and the solid-state sealing resin (17) containing a phosphor (19) are arranged in recesses in package resin (14) having LED chips placed thereon, are thereafter melted by heating, and, in addition, are cured by heating.

Abstract: A light emitting device includes an epitaxial structure and a sheet-shaped wavelength converting layer. The sheet-shaped wavelength converting layer is disposed on the epitaxial structure and at least includes a first wavelength converting unit layer and a second wavelength converting unit layer. The first wavelength converting unit layer is disposed between the second wavelength converting unit layer and the epitaxial structure. An emission peak wavelength of the first wavelength converting unit layer is greater than an emission peak wavelength of the second wavelength converting unit layer. A full width half magnitude of the second wavelength converting unit layer is greater than a full width half magnitude of the first wavelength converting unit layer.

Abstract: A structure includes an SRAM cell includes a first and a second pull-up MOS device, and a first and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. A first metal layer is over the gate electrodes of the MOS devices in the SRAM cell. The structure further includes a first metal layer, and a CVss landing pad, wherein the CVss landing pad has a portion in the SRAM cell. The CVss landing pas is in a second metal layer over the first metal layer. A word-line is in the second metal layer. A CVss line is in a third metal layer over the second metal layer. The CVss line is electrically coupled to the CVss landing pad.

Abstract: The disclosed technology provides micro-assembled micro-LED displays and lighting elements using arrays of micro-LEDs that are too small (e.g., micro-LEDs with a width or diameter of 10 ?m to 50 ?m), numerous, or fragile to assemble by conventional means. The disclosed technology provides for micro-LED displays and lighting elements assembled using micro-transfer printing technology. The micro-LEDs can be prepared on a native substrate and printed to a display substrate (e.g., plastic, metal, glass, or other materials), thereby obviating the manufacture of the micro-LEDs on the display substrate. In certain embodiments, the display substrate is transparent and/or flexible.

Abstract: A vertically stacked heterostructure device includes: (1) a substrate; and (2) vertically stacked layers disposed over the substrate and including (a) a source electrode including a layer of graphene; (b) a drain electrode; and (c) a semiconducting channel disposed between the source electrode and the drain electrode. During operation of the device, a current is configured to flow between the source electrode and the drain electrode through the semiconducting channel.

Abstract: An electrostatic discharge (ESD) unit is described, including a first device, and a second device coupled to the first device in parallel. In an ESD event, the first device is turned on before the second device is turned on. The second device may be turned on by the turned-on first device to form an ESD path in the ESD event.

Abstract: A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low energy, and implanting phosphorus at a low dose and high energy. A thermal drive process diffuses and activates both the heavy dopants and the phosphorus. The antimony and arsenic do not diffuse significantly, maintaining a narrow profile for a main layer of the buried layer. The phosphorus diffuses to provide a lightly-doped layer several microns thick below the main layer. An epitaxial p-type layer is grown over the buried layer.

Abstract: A microelectromechanical system (MEMS) microphone package including a MEMS microphone die configured to sense acoustic pressure and to generate a signal based on the acoustic pressure. An application specific integrated circuit (ASIC) electrically connects to the MEMS microphone die. The MEMS microphone package includes a molded package spacer that connects to a conductive lid and to a substrate. The molded package spacer forms side walls of the MEMS microphone package and is adapted to route electrical connections from the MEMS microphone die and the ASIC to the substrate.