Patents Examined by Neil Prasad
  • Patent number: 10084101
    Abstract: An optical system and photo sensor pixel are provided. The photo sensor pixel includes a substrate including an active region and a peripheral region that is peripheral to the active region, an optical sensor disposed at the active region of the substrate and configured to receive light and output a measurement signal based on the received light, and an encapsulation layer disposed over the active region and the first peripheral region of the substrate. The encapsulation layer includes at least one subwavelength-based graded index structure provided over the peripheral region of the substrate, and the subwavelength-based graded index structure is configured to redirect the light from a region over the peripheral region onto the optical sensor.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: September 25, 2018
    Assignee: Infineon Technologies AG
    Inventors: Thoralf Kautzsch, Heiko Froehlich, Maik Stegemann, Mirko Vogt
  • Patent number: 10079311
    Abstract: A TFT substrate includes a substrate and a plurality of TFTs on the substrate. Each TFT includes a channel layer, a source electrode and a drain electrode on opposite sides of the channel layer. An ohmic contact layer is applied between the channel layer and the source electrode, and between the channel layer and the drain electrode. Both the channel layer and the ohmic contact layer are made of a metal oxide containing zinc. The channel layer has a zinc atomic percentage of less than 35%, and the ohmic contact layer has a zinc atomic percentage of more than 65%.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: September 18, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Hua Lin, Yi-Chun Kao
  • Patent number: 10074702
    Abstract: An organic light emitting diode display panel is disclosed, which comprises: a substrate having a light emitting region and a non-light emitting region, wherein a first electrode layer is disposed on the light emitting region, a pixel defining layer is disposed on the non-light emitting region, and the pixel defining layer has a plurality of concave structures; an organic layer disposed on the first electrode layer and the pixel defining layer; and a second electrode layer disposed on the organic layer; wherein the organic layer is discontinuous at the concave structures.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: September 11, 2018
    Assignee: INNOLUX CORPORATION
    Inventors: Wei-Chieh Teng, Jin-Ju Lin, Neng-Jung You, Wei-Chih Yang
  • Patent number: 10069100
    Abstract: An electronic device may have a display. The device and display may bend about a bend axis. The display may have layers such as an organic light-emitting diode layer or other layer with pixels, a touch sensor layer, a protective layer with a polarizer, and a support layer. Lubrication layers formed from textured surfaces, slippery coatings, and lubricants such as oil may be interposed between the layers of the display so that the display layers slip past each other during bending of the device and display and minimize display stress. A device housing may have a recess or other structures that retain the display within the housing while allowing the display layers to shift relative to each other during bending. Elastomeric gaskets and elastomeric lubricant retention structures may be used to mount the display layers in the housing and to retain liquid lubricant within the layers of the display.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: September 4, 2018
    Assignee: Apple Inc.
    Inventors: Zhen Zhang, Paul S. Drzaic
  • Patent number: 10050185
    Abstract: An illumination device is manufactured by providing (101) a substrate (1) having a first side (1a), sealingly coupling (106) an at least partially light transmitting cover (2) to the substrate (1) such that an enclosed space (3) is defined by at least the first side (1a) of the substrate (1) and the cover (2), providing a through-hole (4) into the enclosed space (3), and introducing (107) a luminescent material into the enclosed space (3) via the through-hole (4). By hermetically sealing (108) the through-hole (4) after the introduction of the luminescent material, the enclosed space (3) becomes sealed and hence luminescent materials being relatively sensitive to e.g. water and/or oxygen become protected from exposure to the environment.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: August 14, 2018
    Assignee: Lumileds LLC
    Inventors: Durandus Kornelius Dijken, Manuela Lunz, Hendrik Johannes Boudewijn Jagt
  • Patent number: 10050108
    Abstract: A semiconductor device may include a semiconductor layer, an insulation gate section, and a first conductivity-type semiconductor region; wherein the semiconductor layer may include a vertical drift region being of a second conductivity type and disposed at the one of main surfaces; a body region being of the first conductivity type, adjoining the vertical drift region, and disposed at the one of main surfaces; and a source region being of the second conductivity type, separated from the vertical drift region by the body region, and disposed at the one of main surfaces, wherein the insulation gate section is opposed to a portion of the body region which separates the vertical drift region and the source region; and the first conductivity-type semiconductor region is opposed to at least a part of a portion of the vertical drift region which is disposed at the one of main surfaces.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 14, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Takashi Okawa
  • Patent number: 10050238
    Abstract: An organic light emitting display device can include a first electrode on a substrate; a first emission part on the first electrode, the first emission part including a first emission layer; a second emission part on the first emission part, the second emission part including a second emission layer; a third emission part on the second emission part, the third emission part including a third emission layer; and a second electrode on the third emission part, in which a first thickness between the substrate and the first emission layer, a second thickness between the first emission layer and the second emission layer, a third thickness between the second emission layer and the third emission layer, and a fourth thickness between the third emission layer and the second electrode are different from each other, and the first, second emission, and third emission parts include at least one organic layer.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 14, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Gwijeong Cho, ChangWook Han, Taeil Kum, Taeshick Kim, Heedong Choi, JiYoung Kim, Mingyu Lee, Taeseok Lim
  • Patent number: 10043709
    Abstract: Methods for selectively depositing a cobalt layer are provided herein. In some embodiments, methods for selectively depositing a cobalt layer include: exposing a substrate to a first process gas to passivate an exposed dielectric surface, wherein the substrate comprises a dielectric layer having an exposed dielectric surface and a metal layer having an exposed metal surface; and selectively depositing a cobalt layer atop the exposed metal surface using a thermal deposition process.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: August 7, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Hua Ai, Jiang Lu, Avgerinos V. Gelatos, Paul F. Ma, Sang Ho Yu, Feng Q. Liu, Xinyu Fu, Weifeng Ye
  • Patent number: 10032672
    Abstract: A method for fabricating a semiconductor device includes the following steps: providing a semiconductor substrate having a first fin; forming a first set of gate structures on the first fin, where the gate structures are surrounded by an interlayer dielectric; forming a first contact hole in the interlayer dielectric between two adjacent gate structures; forming a first dopant source layer on the bottom of the first contact hole, where the dopant source layer comprise dopants with a first conductivity type; and annealing the first dopant source layer to diffuse the dopants out of the first dopant source layer.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: July 24, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Shih-Hung Tsai, Chorng-Lih Young
  • Patent number: 10032695
    Abstract: A semiconductor package includes a substrate, an integrated circuit disposed on the substrate, a memory support disposed on the integrated circuit, stacked memory disposed on the memory support and in communication with the integrated circuit, and a lid connected to the substrate. The integrated circuit has a low power region and a high power region. The memory support is disposed on the low power region of the integrated circuit and is configured to allow a flow of fluid therethrough to conduct heat away from the low power region of the integrated circuit. The lid defines a first port, a second port, and a lid volume fluidly connecting the first port and the second port. The lid volume is configured to house the integrated circuit, the memory support, and the stacked memory, while directing the flow of fluid to flow over the integrated circuit, the memory support, and the stacked memory.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: July 24, 2018
    Assignee: Google LLC
    Inventors: Madhu Krishnan Iyengar, Teck-Gyu Kang, Christopher Gregory Malone, Norman Paul Jouppi
  • Patent number: 10026829
    Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Stephen M. Cea, Tahir Ghani, Harry Gomez, Jack T. Kavalieros, Patrick H. Keys, Seiyon Kim, Kelin J. Kuhn, Aaron D. Lilak, Rafael Rios, Mayank Sahni
  • Patent number: 10008485
    Abstract: A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: June 26, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai, Li-Hui Cheng, Porter Chen
  • Patent number: 9997576
    Abstract: To provide a display device with a manufacturing yield and/or a display device with suppressed mixture of colors between adjacent pixels. The display device includes a first pixel electrode, a second pixel electrode, a first insulating layer, a second insulating layer, and an adhesive layer. The first insulating layer includes a first opening. The second insulating layer includes a second opening. The first opening and the second opening are provided between the first pixel electrode and the second pixel electrode. In a top view, a periphery of the second opening is positioned on an inner side than a periphery of the first opening. The adhesive layer has a region overlapping with the second insulating layer below the second insulating layer.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: June 12, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiro Jinbo, Kohei Yokoyama, Yuki Tamatsukuri, Naoto Goto, Masami Jintyou, Masayoshi Dobashi, Masataka Nakada, Akihiro Chida, Naoyuki Senda
  • Patent number: 9997503
    Abstract: The composite substrate includes: a lead frame including one or more pairs of support leads, each of the one or more pairs of support leads including a first support lead and a second support lead; and one or more packages supported by first and second support leads and including a resin molded body. The resin molded body includes: a first outer side surface; a second outer side surface; a third outer side surface; a fourth outer side surface; a front surface; a first recess; a second recess; a third recess disposed at a bottom surface of the first recess; and a fourth recess disposed at a bottom surface of the second recess. The first support lead is fitted into the first recess and the third recess, and the second support lead is fitted into the second recess and the fourth recess.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: June 12, 2018
    Assignee: NICHIA CORPORATION
    Inventor: Hideaki Tosuke
  • Patent number: 9991469
    Abstract: According to one embodiment, a display device includes an insulating substrate including a first area and a second area adjacent to the first area, the insulating substrate including a first through hole formed in the second area which is formed thinner than the first area, a pad electrode disposed above the first through hole, a signal line electrically connected to the pad electrode, a line substrate including a connection line and disposed below the insulating substrate, a conductive material disposed inside the first through hole to electrically connect the pad electrode and the connection line, a first protection member disposed below the first area, and a second protection member disposed below the first protection member.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: June 5, 2018
    Assignee: Japan Display Inc.
    Inventors: Takumi Sano, Yasushi Kawata
  • Patent number: 9978836
    Abstract: Structures and fabrication methods for vertical-transport field-effect transistors. A nanostructure, a gate structure coupled with the nanostructure, and a source/drain region coupled with an end of the nanostructure are formed. The source/drain region is comprised of a first layer of a first semiconductor material having a first electronic band gap and a second layer of a second semiconductor material having a second electronic band gap that is wider than the first electronic band gap of the first semiconductor material.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: May 22, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Bartlomiej J. Pawlak
  • Patent number: 9966418
    Abstract: The present invention discloses a pixel structure, an organic light emitting display panel and a method for fabricating the same, and a display device. The pixel structure includes a plurality of organic light emitting diodes capable of emitting light of multiple colors and a plurality of light filtering portions provided at a light emitting side of the plurality of organic light emitting diodes, wherein each light filtering portion is provided in correspondence with each of a part of the organic light emitting diodes, such that light emitted from each of the part of the organic light emitting diodes passes through corresponding light filtering portion while light emitted from the remaining of the organic light emitting diodes does not pass through any light filtering portion, and the light filtering portions each process light having a color corresponding to the color of light emitted by corresponding organic light emitting diode.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: May 8, 2018
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Chinlung Liao, Guang Yan
  • Patent number: 9966550
    Abstract: The present invention provides an organic EL element having high luminous efficacy and productivity and an organic EL panel including the organic EL element. The organic electroluminescent element of the present invention includes, in the given order, an anode, a hole-transport layer, a luminescent unit, an electron-transport layer, and a cathode. The luminescent unit includes a mixed light-emitting layer and includes a luminescent dopant layer at least between the hole-transport layer and the mixed light-emitting layer or between the electron-transport layer and the mixed light-emitting layer. The mixed light-emitting layer contains a first luminescent host material and a first luminescent dopant material. The luminescent dopant layer consists essentially of a second luminescent dopant material and is thinner than the mixed light-emitting layer.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: May 8, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yuto Tsukamoto, Katsuhiro Kikuchi, Shinichi Kawato, Hideki Uchida, Manabu Niboshi, Satoshi Inoue, Yoshiyuki Isomura
  • Patent number: 9935232
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes a step of grinding to thin a first semiconductor wafer on which a semiconductor device is formed in a state in which a surface of a second semiconductor wafer is fixed on a chuck table of a grinding device after bonding the first semiconductor wafer to the second semiconductor wafer. The method includes a step of fixing a surface of the first semiconductor wafer on the chuck table and grinding the surface of the second semiconductor wafer in a state in which the first semiconductor wafer is bonded to the second semiconductor wafer prior to the grinding step to thin the first semiconductor wafer.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: April 3, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Gen Toyota, Shouta Inoue, Susumu Yamamoto, Takamasa Tanaka, Takamitsu Yoshida, Kazumasa Tanida
  • Patent number: 9911905
    Abstract: A method of producing an optoelectronic component includes providing a substrate with an optoelectronic semiconductor chip arranged on a surface of the substrate; providing a mask having a lower layer and an upper layer, wherein the lower layer has a lower opening and the upper layer has an upper opening, which openings jointly form a continuous mask opening, and the lower opening has a larger area than the upper opening; arranging the mask above the surface of the substrate such that the lower layer faces the surface of the substrate and the mask opening is arranged above the optoelectronic semiconductor chip; spraying a layer onto the optoelectronic semiconductor chip through the mask opening; and removing the mask.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: March 6, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Markus Richter