Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.

Abstract: A micromechanical sensor device includes: a MEMS element; an ASIC element; a bonding structure provided between the MEMS element and the ASIC element; a layer assemblage having insulating layers and functional layers disposed alternatingly on one another; a sensing element movable in a sensing direction provided in at least one of the functional layers; a spacing element for providing a defined spacing between the MEMS element and the ASIC element being provided by way of a further functional layer; an abutment element having the spacing element and a first bonding layer being disposed on the sensing element; and an insulating layer being disposed on the ASIC element in an abutment region of the abutment element.

Abstract: Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM).

Abstract: A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die.

Abstract: A light emitting device includes a substrate, an electrode connection layer, an epitaxial structure and a plurality of pads. The substrate has an upper surface, a lower surface and a plurality of conductive through holes. The electrode connection layer is disposed on the upper surface of the substrate, and connects with the conductive through holes. An edge of the electrode connection layer is aligned with an edge of the substrate. The epitaxial structure is disposed on the electrode connection layer and electrically connected to the electrode connection layer. The pads are disposed on the lower surface of the substrate and connect with the conductive through holes.

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

Abstract: According to various embodiments, a semiconductor device may include: a layer stack formed at a surface of the semiconductor device, the layer stack including: a metallization layer including a first metal or metal alloy; a protection layer covering the metallization layer, the protection layer including a second metal or metal alloy, wherein the second metal or metal alloy is less noble than the first metal or metal alloy.

Abstract: A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.

Abstract: High-efficiency line-forming optical systems and methods for defect annealing and dopant activation are disclosed. The system includes a CO2-based line-forming system configured to form at a wafer surface a first line image having between 2000 W and 3000 W of optical power. The line image is scanned over the wafer surface to locally raise the temperature up to a defect anneal temperature. The system can include a visible-wavelength diode-based line-forming system that forms a second line image that can scan with the first line image to locally raise the wafer surface temperature from the defect anneal temperature to a spike anneal temperature. Use of the visible wavelength for the spike annealing reduces adverse pattern effects and improves temperature uniformity and thus annealing uniformity.

Abstract: Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bit line contact. The storage node contact plug hole can be cleaned to remove a natural oxide formed in the storage node contact plug hole. Related devices are also disclosed.

Abstract: A microfabricated optical apparatus that includes a light source driven by a waveform, a turning mirror, and a beam shaping element, wherein the waveform is delivered to the light source by at least one through silicon via.

Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

Abstract: A light emitting device has a plurality of light emitting elements that are arranged with gaps between the devices on a mounting board in a first direction, a wavelength-conversion member that covers the plurality of light emitting elements, a light reflective resin. Each light emitting element has an n-type semiconductor layer, an active layer provided in a part of the n-type semiconductor layer, and a p-type semiconductor layer provided on the active layer. In a second direction which is perpendicular to the first direction, an n-side electrodes are provided at least in regions at both ends of the n-type semiconductor layer, and a p-side electrode is provided on the surface of the p-type semiconductor layer, and wherein in the second direction, the wavelength-conversion member is positioned to approximately align both sides with both active layer side faces, or to dispose its sides outward of the active layer side faces.

Abstract: A semiconductor device of an embodiment includes a p-type SiC layer; a SiC region provided on the p-type SiC layer and containing H (hydrogen) or D (deuterium) in an amount of 1×1018 cm?3 or more and 1×1022 cm?3 or less; and a metal layer provided on the SiC region.

Abstract: Method and apparatus for processing audio signals are provided. The method for decoding an audio signal includes extracting a downmix signal and spatial information from a received audio signal, generating surround converting information using the spatial information and rendering the downmix signal to generate a pseudo-surround signal in a previously set rendering domain, using the surround converting information. The apparatus for decoding an audio signal includes a demultiplexing part extracting a downmix signal and spatial information from a received audio signal, an information converting part generating surround converting information using the spatial information and a pseudo-surround generating part rendering the downmix signal to generate a pseudo-surround signal in a previous set rendering domain, using the surround converting information.

Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.

Abstract: A crystalline oxide semiconductor film and a semiconductor device including the oxide semiconductor film are provided. One embodiment of the present invention is an oxide semiconductor film including a plurality of flat-plate particles each having a structure in which layers including a gallium atom, a zinc atom, and an oxygen atom are provided over and under a layer including an indium atom and an oxygen atom. In the semiconductor film, the plurality of flat-plate particles face in random directions, and a crystal boundary is not observed using a transmission electron microscope.

Abstract: A first substrate, bonded to a second substrate by a material, is provided. The first substrate is transparent to at least some wavelengths of electromagnetic radiation. The first substrate is irradiated with the electromagnetic radiation to which the first substrate is transparent, such that the electromagnetic radiation impinges on the material causing a decomposition thereof at a location at an interface between the first substrate and the material. The decomposition results in, at the location, an interface of the first substrate and an atmosphere of the decomposition. The atmosphere of the decomposition has an optical property resulting in ceasing the decomposition of the material.

Abstract: A method for controlling a semiconductor fabrication process includes the steps of analyzing process-data related to an intermediate-process-step in the fabrication process and adjusting a metal-layer-parameter corresponding to the metal layer based on the process-data.

Abstract: The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device.