Abstract: Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.

Abstract: A semiconductor device, comprising: a substrate which includes an active circuit region, and a boundary region surrounding the active circuit region, the boundary region including an edge portion of the substrate; a first lower conductive pattern disposed on the substrate of the boundary region; and a first upper conductive pattern connected to the first lower conductive pattern over the first lower conductive pattern, wherein the first upper conductive pattern includes a first portion having a first thickness, a second portion having a second thickness greater than the first thickness, and a third portion having a third thickness greater than the second thickness, and the third portion of the first upper conductive pattern is connected to the first lower conductive pattern, is provided.

Abstract: Hybrid trigate and nanowire CMOS device architecture, and methods of fabricating hybrid trigate and nanowire CMOS device architecture, are described. For example, a semiconductor structure includes a semiconductor device of a first conductivity type having a plurality of vertically stacked nanowires disposed above a substrate. The semiconductor structure also includes a semiconductor device of a second conductivity type opposite the first conductivity type, the second semiconductor device having a semiconductor fin disposed above the substrate.

Abstract: A semiconductor package including at least one semiconductor device, a first redistribution layer, a first molding compound, a second molding compound, conductive vias and a second redistribution layer. The first redistribution layer is disposed beneath the semiconductor device and electrically connected to the semiconductor device. The first molding compound is disposed over the first redistribution layer and surrounds the semiconductor device. The second molding compound surrounds the first redistribution layer and at least a part of the first molding compound. The conductive vias extend through the second molding compound. The second redistribution layer is disposed on a surface of the second molding compound away from the first redistribution layer. The second redistribution layer is electrically connected to the first redistribution layer through the conductive vias.

Abstract: Packaged semiconductor die and CTE-engineering die pairs and methods to form packaged semiconductor die and CTE-engineering die pairs are described. For example, a semiconductor package includes a substrate. A semiconductor die is embedded in the substrate and has a surface area. A CTE-engineering die is embedded in the substrate and coupled to the semiconductor die. The CTE-engineering die has a surface area the same and in alignment with the surface area of the semiconductor die.

Abstract: The present disclosure provides a carbon nanotube thin film transistor (CNT-TFT) and its manufacturing method. The carbon nanotube thin film transistor includes a source electrode, a drain electrode, a channel region, a plurality of protrusions, and a carbon nanotube layer. The channel region is between the source electrode and the drain electrode. The plurality of protrusions are at, and extend in a length direction of, the channel region. The carbon nanotube layer is disposed over the plurality of protrusions, and comprises a plurality of carbon nanotubes.

Abstract: A semiconductor device including a stacked assembly. The stacked assembly includes a metal substrate, a stacked substrate mounted on the metal substrate and having an electrode pattern, a semiconductor element mounted on the stacked substrate, and a lead frame interconnection electrically connecting the semiconductor element and the electrode pattern. The lead frame interconnection includes a first bonding portion in contact with the semiconductor element, a second bonding portion in contact with the electrode pattern, and an interconnect portion connecting the first and second bonding portions. At least one of the first bonding portion and the second bonding portion is wider than the interconnect portion.

Abstract: An image sensor and a method for fabricating the same are provided, in which the image sensor includes a substrate including a first sensing region having a photoelectric device therein, a boundary isolation film partitioning the first sensing region, an inner reflection pattern film within the substrate in the sensing region, an infrared filter on the substrate, and a micro lens on the infrared filter.

Abstract: In the manufacture of a semiconductor device, electrical interconnects are formed by depositing a dielectric layer over source/drain regions, and forming a continuous trench within the dielectric layer. The trench may traverse plural source/drain regions associated with adjacent devices. The electrical interconnects are thereafter formed by metallizing the trench and patterning the metallization layers to form discrete interconnects over and in electrical contact with respective source/drain regions. The source/drain interconnects exhibit a reentrant profile, which presents a larger contact area to later-formed conductive contacts than a conventional tapered profile, and thus improve manufacturability and yield.

Abstract: A photoelectric conversion element according to an embodiment of the present disclosure includes: a first electrode and a second electrode facing each other; and a photoelectric conversion layer provided between the first electrode and the second electrode, and including a first organic semiconductor material, a second organic semiconductor material, and a third organic semiconductor material that have mother skeletons different from one another. The first organic semiconductor material is one of fullerenes and fullerene derivatives. The second organic semiconductor material in a form of a single-layer film has a higher linear absorption coefficient of a maximal light absorption wavelength in a visible light region than a single-layer film of the first organic semiconductor material and a single-layer film of the third organic semiconductor material. The third organic semiconductor material has a value equal to or higher than a HOMO level of the second organic semiconductor material.

Abstract: Disclosed herein is an electronic circuit package that includes a substrate having a power supply pattern, an electronic component mounted on a surface of the substrate; and a molding member having conductivity that covers the surface of the substrate so as to embed the electronic component therein. The power supply pattern includes a first power supply pattern exposed to the surface of the substrate, and the molding member contacts the first power supply pattern.

Abstract: In some embodiments, the present disclosure relates to an image sensor integrated chip. The integrated chip has an image sensing element arranged within a pixel region of a substrate. A first dielectric is disposed in trenches within a first side of the substrate. The trenches are defined by first sidewalls disposed on opposing sides of the pixel region. An internal reflection enhancement structure is arranged along the first side of the substrate and is configured to reflect radiation exiting from the substrate back into the substrate.

Abstract: An array substrate and a method of manufacturing the array substrate are provided. The method includes providing a substrate, sequentially forming a light-shielding layer, a buffer layer, an active layer, a source, a drain, a gate insulating layer, and a gate on the substrate, performing a first conductorization process on a corresponding region of the active layer opposite to the source and the drain, and performing a second conductorization process on another corresponding region of the active layer between the source and the gate and between the drain and the gate.

Abstract: A semiconductor chip module includes a chip unit including first and second semiconductor chips formed over a single body to be adjacent in a first direction with a scribe line region interposed therebetween, and having a first surface over which bonding pads of the first and second semiconductor chips are positioned; redistribution lines formed over the first surface, having one set of ends which are respectively electrically coupled to the bonding pads, and extending in a direction oblique to the first direction toward the scribe line region; and redistribution pads disposed over the first surface, and electrically coupled with another set of ends of the redistribution lines.

Abstract: A photovoltaic device (1) includes: an i-type amorphous semiconductor layer (102i) formed in contact with one of the surfaces of a semiconductor substrate (101); p-type amorphous semiconductor strips (102p) spaced apart from each other and provided on the i-type amorphous semiconductor layer (102i); and n-type amorphous semiconductor strips (102n) spaced apart from each other and provided on the i amorphous semiconductor layer (102i), each n-type amorphous semiconductor strip (102n) being adjacent to at least one of the p-type amorphous semiconductor strips (102p) as traced along an in-plane direction of the semiconductor substrate (101). The photovoltaic device (1) further includes electrodes (103) as a protection layer formed in contact with the i-type amorphous semiconductor layer (102) between adjacent p-type amorphous semiconductor strips (102p) and between adjacent n-type amorphous semiconductor strips (102n).

Abstract: An optical system and photo sensor pixel are provided. The photo sensor pixel includes a substrate including an active region and a peripheral region that is peripheral to the active region, an optical sensor disposed at the active region of the substrate and configured to receive light and output a measurement signal based on the received light, and an encapsulation layer disposed over the active region and the first peripheral region of the substrate. The encapsulation layer includes at least one subwavelength-based graded index structure provided over the peripheral region of the substrate, and the subwavelength-based graded index structure is configured to redirect the light from a region over the peripheral region onto the optical sensor.

Abstract: An avalanche photodetector (APD) includes a photo converter for signals to be demodulated into free charge carriers; and at least one avalanche amplifier for the free charge carriers. The photo converter and the avalanche amplifier are located next to each other on the same substrate and are in direct contact with each other. The avalanche amplifier includes a contact layer and a multiplier layer. The multiplier layer is made of a semiconductor of the same conductivity type as the photo converter and faces the substrate abutting the photo converter on one side. A first electrode is on the contact layer of the avalanche amplifier, while the second electrode is on a bottom of the substrate.

Abstract: Embodiments relate to a flexible organic light emitting diode (OLED) display device and a method for manufacturing the flexible OLED display device. The display device includes a multi-layered encapsulation film coving pixel regions of the display device, and a metal layer on or within at least a portion of the encapsulation film, the portion in a bending region of the flexible substrate. The multi-layered encapsulation film includes at least a first inorganic layer, an organic layer, and a second inorganic layer. The metal layer is formed in the bending region such that the stress generated in the encapsulation film by folding, bending, or rolling operations in the bending region is reduced by the metal layer. The metal layer prevents generation of cracks in the encapsulation film and thus, prevents moisture penetration into the display area of the display device.

Abstract: An image sensor package, comprising a silicon substrate; an image sensor pixel array that is formed on the silicon substrate; a peripheral circuit region that is formed around the image sensor pixel array on the silicon substrate; a redistribution layer (RDL) that is electrically coupled to the peripheral circuit region; at least one solder ball that is electrically coupled to the RDL; and a cover glass that is coupled to the RDL. No part of the RDL is located directly above or below the image sensor pixel array. No part of the at least one solder ball is located directly above or below the silicon substrate. A dark material layer is implemented to prevent an edge flare effect of the image sensor pixel array.

Abstract: To provide a display device with a manufacturing yield and/or a display device with suppressed mixture of colors between adjacent pixels. The display device includes a first pixel electrode, a second pixel electrode, a first insulating layer, a second insulating layer, and an adhesive layer. The first insulating layer includes a first opening. The second insulating layer includes a second opening. The first opening and the second opening are provided between the first pixel electrode and the second pixel electrode. In a top view, a periphery of the second opening is positioned on an inner side than a periphery of the first opening. The adhesive layer has a region overlapping with the second insulating layer below the second insulating layer.