Abstract: A semiconductor wafer to be treated is placed on a susceptor made of quartz installed in a chamber, and is heated by light irradiation from halogen lamps. Before the first semiconductor wafer of a production lot is transported into the chamber, a preheating substrate is placed on the susceptor. Then, the preheating substrate is heated by light irradiation from the halogen lamps to preheat the susceptor. The susceptor is heated to a preheating temperature higher than a stable temperature when the semiconductor wafers of the production lot are continuously treated. This enables a structure in the chamber, other than the susceptor, to be preheated to a temperature during steady treatment of the semiconductor wafer in a short time, so that it is possible to eliminate dummy running for heating the structure in the chamber by applying heating treatment to a plurality of dummy wafers.

Abstract: A synthetic quartz glass lid is provided comprising a synthetic quartz glass and an adhesive formed on a periphery of a main surface of the window member. Further, an optical device package is provided comprising a box-shaped receptacle having an open upper end, an optical device received in the receptacle, and a window member of synthetic quartz glass bonded to the upper end of the receptacle with an adhesive. The adhesive is a low-melting metallic glass consisting of Te, Ag and at least one element selected from W, V, P, Ba, and Zr.

Abstract: A semiconductor device includes a semiconductor substrate including an in-cell area and a scribe lane defining the in-cell area, a first overlay pattern on the semiconductor substrate, and a second overlay pattern adjacent to the first overlay pattern, wherein the first overlay pattern is a diffraction-based overlay (DBO) pattern and the second overlay pattern is a scanning electron microscope (SEM) overlay pattern.

Abstract: Certain aspects of the present disclosure provide a variable transistor-based capacitive element implemented on a glass or dielectric substrate. Such a variable transistor-based capacitive element may be suitable for use as a tunable capacitor in a passive-on-glass (POG) device, for example. One example device having a tunable capacitance generally includes a glass or dielectric substrate and a transistor disposed above the glass or dielectric substrate. The transistor has a gate region, a drain region, and a source region, wherein a capacitance of the transistor is configured to vary based on a voltage between the gate region and the drain region.

Abstract: A four-terminal GaN transistor and methods of manufacture, the transistor having source and drain regions and preferably two T-shaped gate electrodes, wherein a stem of one of the two T-shaped gate electrodes is more closely located to the source region than it is to a stem of the other one of the two T-shaped gate electrodes and wherein the stem of the other one of the two T-shaped gate electrodes is more closely located to the drain region than it is to the stem of said one of the two T-shaped gate electrodes. The the gate closer to the source region is a T-gate, and the proximity of the two gates is less than 500 nm from each other. The spacing between the stem of the RF gate and source region and the stem of the DC gate and drain region are preferably defined by self-aligned fabrication techniques. The four-terminal GaN transistor is capable of operation in the W-band (75 to 100 GHz).

Abstract: A light emitting apparatus according to an embodiment of the present technology includes a base portion, a light emitting element, and a cover portion. The base portion includes a support surface. The light emitting element is disposed on the support surface of the base portion. The cover portion includes a light transmission portion through which light emitted from the light emitting element is transmitted and a protrusion portion which is provided on at least a part of a periphery of the light transmission portion and protruded relative to the light transmission portion, the cover portion being provided on the support surface in such a manner as to cover the light emitting element.

Abstract: This disclosure relates to a semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device structure comprises a semiconductor substrate having an edge region laterally separated from a device region; an edge termination structure arranged on the semiconductor substrate; wherein the edge termination structure comprises: a first oxide layer arranged on the substrate to extend from the active region to the edge region; an isolation layer arranged on top of the first oxide layer; and a metal layer arranged to at least partially cover the isolation layer and wherein the metal layer is further arranged to extend from the isolation layer to contact the edge region.

Abstract: An image sensor and a method for fabricating the same are provided, in which the image sensor includes a substrate including a first sensing region having a photoelectric device therein, a boundary isolation film partitioning the first sensing region, an inner reflection pattern film within the substrate in the sensing region, an infrared filter on the substrate, and a micro lens on the infrared filter.

Abstract: According to an aspect, a stack packaging structure includes a substrate, a semiconductor device coupled to a surface of the substrate, an image sensor device coupled to the semiconductor device such that the semiconductor device is disposed between the surface of the substrate and the image sensor device, at least one bond wire connected to the image sensor device and the surface of the substrate, a inner molding disposed between the surface of the substrate and the image sensor device, where the semiconductor device is encapsulated within the inner molding, and an outer molding disposed on the surface of the substrate, where the at least one bond wire is encapsulated within the outer molding.

Abstract: According to an aspect, a multi-chip packaging structure includes a first substrate having a first surface and a second surface, where the first substrate has a conductive layer portion. The multi-chip packaging structure includes an image sensor device coupled to the first surface of the first substrate, a first device coupled to the second surface of the first substrate, and a second substrate disposed apart from the first substrate, where the second substrate has a conductive layer portion. The conductive layer portion of the first substrate is communicatively connected to the conductive layer portion of the second substrate. The first device is disposed between the first substrate and the second substrate. The multi-chip packaging structure includes a second device coupled to the second substrate, and a third device coupled to the first substrate or the second substrate.

Abstract: An array substrate for a digital X-ray detector and the digital X-ray detector including the same are disclosed. The array substrate effectively protects a PIN diode from external moisture or water, maximizes a light transmission region of a PIN diode, and reduces resistance by maximizing the region of a bias wiring. To this end, a closed-loop bias electrode formed to cover a circumferential surface of a PIN diode is used. In detail, the bias electrode includes a closed loop portion and a contact extension portion. The contact extension portion extends from one end of the closed loop portion so as to directly contact an upper electrode, and includes a hollow part therein.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a gate structure on a base substrate and forming a first dielectric layer on the base substrate. The first dielectric layer has a top lower than the gate structure and exposes a sidewall portion of the gate structure. The method also includes forming an isolation sidewall spacer on the exposed sidewall portion of the gate structure.

Abstract: A light source includes a plurality of semiconductor components, wherein a semiconductor component includes a plurality of light-emitting diodes, the diodes are arranged in a predefined grid in at least one column in or on the semiconductor component, and a control circuit that drives the individual diodes is arranged on the semiconductor component.

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

Abstract: A capacitor cell for a semiconductor device, wherein the capacitor cell comprises: a capacitor having a first node and a second node; a first electrode structure, comprising a first contact point and a second contact point, wherein the first contact point and the second contact point are electrically connected to the first node of said capacitor and located at two different edges of the capacitor cell; and a second electrode structure, comprising a third contact point and a fourth contact point, wherein the third contact point and the fourth contact point are electrically connected to the second node of said capacitor and located at said two different edges of the capacitor cell.

Abstract: A semiconductor device, which is a diode, includes the following: an n cathode layer, which is an n-type region, disposed in a surface layer of a semiconductor substrate; a p cathode layer, which is a p-type region, disposed in the surface layer; and a cathode electrode, which is a metal electrode, in contact with both of the n cathode layer and the p cathode layer. The cathode electrode includes a first metal layer in contact with both of the n cathode layer and the p cathode layer, and a second metal layer disposed on the first metal layer. A contact surface between the first metal layer and the second metal layer has an oxygen concentration lower than the oxygen concentration of a contact surface between the first metal layer, and the n cathode layer and the p cathode layer.

Abstract: An image sensor and a method for fabricating the same are provided, in which the image sensor includes a substrate including a first sensing region having a photoelectric device therein, a boundary isolation film partitioning the first sensing region, an inner reflection pattern film within the substrate in the sensing region, an infrared filter on the substrate, and a micro lens on the infrared filter.

Abstract: An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.

Abstract: The present disclosure provides a mask assembly and a method for manufacturing the same, and a display device. The mask assembly includes a frame, a first mask and a second mask, and the first mask and the second mask are superposed on the frame; the first mask includes an opening region, the second mask includes an evaporation region in which a first evaporation hole is provided for allowing an evaporation material to pass therethrough and a buffer region surrounding the evaporation region and configured to block off the evaporation material, and an orthographic projection of the boundary of the opening region onto the second mask is located within the buffer region.

Abstract: A first bit line structure is disposed between a first contact structure and a second contact structure. A first air spacer is interposed between the first contact structure and the first bit line structure. A first separation space is connected to an air entrance of the first air spacer and interposed between the first contact structure and the first bit line structure. A cover insulating pattern with a gap portion is interposed between the first contact structure and the second contact structure. The gap portion has a downwardly-decreasing width. An air capping pattern covers the cover insulating pattern to seal the first separation space.