Abstract: Methods of forming a metal resistor are provided. The methods may include: depositing a metal layer, e.g., tungsten, on a substrate; and forming the metal resistor by implanting a semiconductor species, e.g., silicon and/or germanium, into the metal layer to form a semiconductor-metal alloy layer from at least a portion of the metal layer. In certain embodiments, an adhesion layer may be deposited by ALD prior to metal layer depositing. The metal resistor has a sheet resistance that remains substantially constant prior to and after subsequent annealing.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device, such as a varactor diode. The IC device includes a composite collector and heterostructure. A layer of wider band gap material is included as part of the collector at the collector/base interface. The presence of the wide band gap material may increase breakdown voltage and allow for increased hyperabrupt doping profiles in the narrower band gap portion of the collector. This may allow for increased tuning range and improved intermodulation (IMD) performance without the decreased breakdown performance associated with homojunction devices. Other embodiments may also be described and/or claimed.

Abstract: An electrostatic discharge device comprises a transistor with one of its source and drain serving as an input terminal of said device and the other serving as an output terminal. Said transistor comprises: a first conductive layer used as a first floating gate; a first insulating layer covering said first conductive layer; an active layer on said first insulating layer; a second insulating layer covering said active layer; a second conductive layer used as a second floating gate and on said second insulating layer; a third insulating layer covering said second conductive layer; a third conductive layer and a fourth conductive layer on said third insulating layer and on both sides of the active layer, said third conductive layer being isolated from the fourth conductive layer, wherein said third conductive layer serves as one of the source and the drain and said fourth conductive layer serves as the other.

Abstract: When forming sophisticated semiconductor devices requiring resistors based on polysilicon material having non-silicided portions, the respective cap material for defining the silicided portions may be omitted during the process sequence, for instance, by using a patterned liner material or by applying a process strategy for removing the metal material from resistor areas that may not receive a corresponding metal silicide. By implementing the corresponding process strategies, semiconductor devices may be obtained with reduced probability of contact failures, with superior performance due to relaxing surface topography upon forming the contact level, and/or with increased robustness with respect to contact punch-through.

Abstract: Methods of forming a semiconductor structure include the use of channeled implants into silicon carbide crystals. Some methods include providing a silicon carbide layer having a crystallographic axis, heating the silicon carbide layer to a temperature of about 300° C. or more, implanting dopant ions into the heated silicon carbide layer at an implant angle between a direction of implantation and the crystallographic axis of less than about 2°, and annealing the silicon carbide layer at a time-temperature product of less than about 30,000° C.-hours to activate the implanted ions.

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace disposed at a first layer-level. A second conductive trace is disposed at a second layer-level. A first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace.

Abstract: A method and corresponding device for the alignment of a first substrate comprising at least two first alignment marks with a second substrate comprising at least two second alignment marks. By means of a first assignment, the first alignment marks are assigned to at least two first characteristic alignment features of the first substrate in an X-direction and in a Y-direction. By means of a second assignment, the second alignment marks are assigned to at least two second characteristic alignment features of the second substrate in an X-direction and in a Y-direction, and by means of an alignment, the first and second alignment marks are aligned in relation to one another in an X- and Y-direction by means of the first and second characteristic alignment features.

Abstract: The present disclosure provides a semiconductor structure, including a first silicon layer having a through silicon via (TSV), a III-V structure over the first silicon layer, electrically coupling to the TSV, and a redistribution layer (RDL) under the first silicon layer, electrically coupling to the TSV. The present disclosure also provides a method of manufacturing a semiconductor device. The method includes providing a III-V-on-Si structure, comprising a III-V device over a silicon layer, forming a through silicon via (TSV) in the silicon layer, electrically coupling to the III-V device, and forming a redistribution layer (RDL) over a side of the silicon layer opposite to the III-V device.