Abstract: The present disclosure provides a mask assembly and a method for manufacturing the same, and a display device. The mask assembly includes a frame, a first mask and a second mask, and the first mask and the second mask are superposed on the frame; the first mask includes an opening region, the second mask includes an evaporation region in which a first evaporation hole is provided for allowing an evaporation material to pass therethrough and a buffer region surrounding the evaporation region and configured to block off the evaporation material, and an orthographic projection of the boundary of the opening region onto the second mask is located within the buffer region.

Abstract: A first bit line structure is disposed between a first contact structure and a second contact structure. A first air spacer is interposed between the first contact structure and the first bit line structure. A first separation space is connected to an air entrance of the first air spacer and interposed between the first contact structure and the first bit line structure. A cover insulating pattern with a gap portion is interposed between the first contact structure and the second contact structure. The gap portion has a downwardly-decreasing width. An air capping pattern covers the cover insulating pattern to seal the first separation space.

Abstract: A display substrate is disclosed, comprising a display area and a peripheral area surrounding the display area. The display substrate is fixed to a counter substrate in the peripheral area by a frame sealant. The display substrate comprises a substrate and a curing energy transmissive layer. A projection of the frame sealant on the substrate falls within or coincides with that of the curing energy transmissive layer. Since the curing energy transmissive layer transparent for the curing energy beam is provided in the display substrate, the frame sealant can be irradiated from the display substrate side through the curing energy transmissive layer, instead of from the counter substrate side. This improves the efficiency for curing the frame sealant. A display panel, a method for fabricating the display substrate and the display panel, and a display device are disclosed.

Abstract: A semiconductor package including at least one semiconductor device, a first redistribution layer, a first molding compound, a second molding compound, conductive vias and a second redistribution layer. The first redistribution layer is disposed beneath the semiconductor device and electrically connected to the semiconductor device. The first molding compound is disposed over the first redistribution layer and surrounds the semiconductor device. The second molding compound surrounds the first redistribution layer and at least a part of the first molding compound. The conductive vias extend through the second molding compound. The second redistribution layer is disposed on a surface of the second molding compound away from the first redistribution layer. The second redistribution layer is electrically connected to the first redistribution layer through the conductive vias.

Abstract: A film forming apparatus is provided for forming a film by revolving a substrate placed on a rotary table in a vacuum container, alternately supplying a precursor gas and a reaction gas that reacts with the precursor gas to generate a reaction product multiple times, and depositing the reaction product on the substrate. The film forming apparatus comprises a precursor gas supply region that supplies the precursor gas onto the substrate, one or more plasma generation regions that generate plasma at a position apart from the precursor gas supply region in a rotational direction of the rotary table, and a cleaning region that cleans the rotary table by supplying a cleaning gas onto the rotary table in a region apart from the plasma generation regions and the precursor gas supply region in the rotational direction when a film forming process is not performed on the substrate.

Abstract: A coaxial nanocomposite including a core, which includes fibers of a first organic polymer, and a shell, which includes fibers of a second organic polymer, the first polymer and the second polymer forming a heterojunction.

Abstract: A converter for an optoelectronic component, an optoelectronic component, a method for forming a converter for an optoelectronic component and a material for a reflector of an optoelectronic component are disclosed. In an embodiment, a converter includes a conversion element for converting a wavelength of electromagnetic radiation which passes through at least a part of the conversion element and a reflector, wherein the reflector includes a reflector material which includes MgF2 and/or an inorganic material as a matrix material in which a plurality of particles is embedded, wherein a refractive index of the matrix material amounts to at least 1 and at most 2, and wherein a refractive index of the particles amounts to at least 1.5.

Abstract: The present invention provides a layout pattern of a static random access memory (SRAM), comprising at least one substrate, two SRAM units on the substrate, respectively located in a first region and a second region which is adjacent to the first region. Each of the SRAM units includes a first inverter coupled to a second inverter and configured to form a latching circuit, the first inverter includes a first pull-up transistor (PU1) and a first pull-down transistor (PD1), the second inverter includes a second pull-up transistor (PU2) and a second pull-down transistor (PD2). A dummy layer crossing the first a region and the second region, and between the PD1 in the first region and the PD1 in the second region, and a contact structure on the dummy layer, electrically connected to a voltage source Vss.

Abstract: A spin current magnetization rotational element includes: a first ferromagnetic metal layer having a variable magnetization direction; and a spin orbital torque wiring which is joined to the first ferromagnetic metal layer and extends in a direction crossing a direction perpendicular to a plane of the first ferromagnetic metal layer, wherein the spin orbital torque wiring is constituted of a non-magnetic material composed of elements of two or more kinds and a compositional proportion of the non-magnetic material has a non-uniform distribution between a first surface joined to the first ferromagnetic metal layer and a second surface located on a side opposite to the first surface.

Abstract: A substrate processing method is provided for metal filling of recessed features in a substrate. According to one embodiment, the method includes providing a substrate containing horizontally spaced nested and isolated recessed features, filling the nested and isolated recessed features with a blocking material, and performing in any order: a) sequentially first, removing the blocking material from the nested recessed features, and second, filling the nested recessed features with a first metal, and b) sequentially first, removing the blocking material from the isolated recessed features, and second, filling the isolated recessed features with a second metal that is different from the first metal. According to one embodiment, the first metal may include Ru metal and the second metal may include Cu metal. According to one embodiment, a microelectronic device containing metal filled recessed features is provided.

Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen. The device further includes an interconnect material layer provided on a surface of the metal layer.

Abstract: A pixel structure of an image sensor is provided and includes following units. A crystalline layer of a first doping type is formed on a substrate. A photodiode region is formed in the crystalline layer. A gate of a source follower transistor is formed on a top surface of the crystalline layer. A reset gate is formed on the top surface of the crystalline layer. A doped region of a second doping type is formed in the crystalline layer and formed between the reset gate and the gate of the source follower. The first doping type is different from the second doping type, and the photodiode region is connected to the doped region under the top surface of the crystalline layer as an anti-blooming path.

Abstract: A tunnel magnetic resistance element includes the following, a fixed magnetic layer with a fixed direction of magnetization, a free magnetic layer in which the direction of magnetization changes, and an insulating layer which is positioned between the fixed magnetic layer and the free magnetic layer. The fixed magnetic layer, the free magnetic layer, and the insulating layer form a magnetic tunnel junction. A resistance of the insulating layer changes by a tunnel effect according to a difference in an angle between the direction of magnetization of the fixed magnetic layer and the direction of magnetization of the free magnetic layer. The free magnetic layer includes a ferromagnetic layer, a soft magnetic layer, and a magnetic bonding layer placed in between. Material of the magnetic bonding layer include Ru or Ta, and a layer thickness is 1.0 nm to 1.3 nm.

Abstract: Described herein is an integrated circuit device comprising a conductive line structure including a bit line and an insulating capping pattern; and an insulating spacer covering a side wall of the conductive line structure, the insulating spacer including an inner spacer and a char spacer. To form the insulating spacer, a polymer brush pattern may be chemically bonded to the inner spacer to cover a side wall of the conductive line structure; a first insulating spacer film covering the inner spacer and the polymer brush pattern may be formed; and a char spacer may be formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen.

Abstract: Some embodiments include an apparatus having a polishing mechanism configured to polish a surface of a wafer. The polishing mechanism converts fresh slurry to used slurry during a polishing process. At least one emitter is configured to direct electromagnetic radiation onto or through the used slurry. At least one detector is configured to detect transmittance of the electromagnetic radiation through the used slurry or reflection of the electromagnetic radiation from the used slurry. An identification system is coupled with the at least one detector and is configured to identify a property of the used slurry indicating that an endpoint of the polishing process has been reached. Control circuitry is coupled with the identification system and is configured to stop the polishing process based on receiving a trigger from the identification system. Some embodiments include polishing methods.

Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.

Abstract: A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die.

Abstract: In some embodiments, the present disclosure relates to an image sensor integrated chip. The integrated chip has an image sensing element arranged within a substrate. A first dielectric is disposed in one or more trenches within a first side of the substrate. The one or more trenches laterally surround the image sensing element. The substrate includes a recessed portion arranged along the first side of the substrate and defined by second sidewalls of the substrate directly over the image sensing element. The second sidewalls of the substrate are angled to meet at a point disposed along a horizontal plane that intersects the first dielectric within the one or more trenches.

Abstract: A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a pixel sensor disposed in the substrate, and a color filter disposed over the pixel sensor. The pixel sensor includes a plurality of first micro structures disposed over the back side of the substrate, and the color filter includes a plurality of second micro structures disposed over the back side of the substrate.

Abstract: Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM).