Abstract: A semiconductor storage device of an embodiment includes: a stacked body in which a plurality of conductive layers are stacked with an insulating layer interposed therebetween, the stacked body having a memory portion in which a plurality of memory cells are disposed and a stepped portion in which ends of the plurality of conductive layers form a step shape; and a conductive portion which extends in the memory portion in a stacking direction of the stacked body inside the plurality of conductive layers from an uppermost conductive layer among the plurality of conductive layers, extends in the stepped portion in the stacking direction of the stacked body inside at least some layers among the plurality of conductive layers, and extends from the memory portion to the stepped portion in a direction intersecting the stacking direction of the stacked body. A height of the conductive portion in the stepped portion is lower than a height of the conductive portion in the memory portion.

Abstract: Overcoming parasitic capacitances in RF integrated circuits is a challenging problem. The disclosed methods and devices provide solution to such challenge. Devices based on tunable capacitive elements that can be implemented with switch RF stacks are also disclosed.

Abstract: An imaging element has at least a photoelectric conversion section, a first transistor TR1, and a second transistor TR2, the photoelectric conversion section includes a photoelectric conversion layer, a first electrode, and a second electrode, the imaging element further has a first photoelectric conversion layer extension section, a third electrode, and a fourth electrode, the first transistor TR1 includes the second electrode that functions as one source/drain section, the third electrode that functions as a gate section, and the first photoelectric conversion layer extension section that functions as the other source/drain section, and the first transistor TR1 (TRrst) is provided adjacent to the photoelectric conversion section.

Abstract: A magnetoresistive element comprises a perpendicular coupling layer between a novel perpendicular AFM layer and ferromagnetic recording layer. The perpendicular coupling layer introduces giant magnetic anisotropy energies (P-MAE) on the recording layer interface and the P-AFM layer interface which further introduce RKKY coupling between the magnetic moment of the recording layer and the P-MAE induced magnetic moment at the P-AFM layer interface, yielding a giant perpendicular magnetic anisotropy of the recording layer.

Abstract: Described is an apparatus which comprises: a die with a first side; a first set of solder balls coupled to the die along the first side; a laminate based substrate adjacent to the first set of solder balls, the laminate based substrate having at least one balun, at least one bandpass filter (BPF), and at least one diplexer embedded in the laminate, wherein the at least one balun is communicatively coupled to the first die via at least one of the solder balls of the first set.

Abstract: Circuits employing an adjacent low-k dummy gate to a field-effect transistor (FET) to reduce FET source/drain parasitic capacitance, and related fabrication methods. To reduce or mitigate an increase in the source/drain parasitic capacitance(s) of a FET, a dummy gate adjacent to an active gate of the FET is provided to have a low-k (i.e., low relative permittivity). In this manner, the relative permittivity (k) between the source/drain of the FET and an adjacent dummy gate and/or source/drain of another FET is reduced, thereby reducing the parallel plate capacitance of the FET(s). Reducing parasitic capacitance of the FET(s) may allow further reduced scaling of the circuit to offset or mitigate a lack of reduction or increase in parasitic capacitance as a result of reducing gate pitch in the circuit. As gate pitch is reduced in the circuit, it may not be possible to proportionally reduce gate size without sacrificing gate control.

Abstract: A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a pixel sensor disposed in the substrate, and a color filter disposed over the pixel sensor. The pixel sensor includes a plurality of first micro structures disposed over the back side of the substrate. The color filter includes a plurality of second micro structures disposed over the back side of the substrate. Each of the first micro structures has a first height, and each of the second micro structures has a second height. The second height is less than the first height.

Abstract: Information handling system thermal rejection of thermal energy generated by one or more components, such as a central processing unit and graphics processing unit, is enhanced by disposing boron arsenide between the one or more components and a heat transfer structure that directs thermal energy from the one or more components to a heat rejection region, such as cooling fan exhaust. For instance, the boron arsenide is a layer formed with chemical vapor deposition on a copper heat pipe or a layer of thermal grease infused with the boron arsenide.

Abstract: Embodiments disclosed herein relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an embodiment, a method includes conformally forming a gate dielectric layer on a fin extending from a substrate and along sidewalls of gate spacers over the fin, conformally depositing a dummy layer over the gate dielectric layer during a deposition process using a silicon-containing precursor and a dopant gas containing fluorine, deuterium, or a combination thereof, the dummy layer as deposited comprising a dopant of fluorine, deuterium, or a combination thereof, performing a thermal process to drive the dopant from the dummy layer into the gate dielectric layer, removing the dummy layer, and forming one or more metal-containing layers over the gate dielectric layer.

Abstract: An electronic device assembly includes one or more discrete electronic components mounted onto a substrate having a 3D, 2.5D, or N×2D geometric classification. The substrate surface includes a specific mounting location to which an electronic component is to be electrically connected, where each specific mounting location includes one or more electrical connection points, such as contact pads. An anisotropic conductive film (ACF) is applied to the substrate surface covering the one or more electrical connection points of the specific mounting location, and the electronic component is placed on the ACF and properly aligned with the specific mounting location on the substrate surface. Pressure and heat are applied to compress the ACF to form an electrical interconnection between corresponding pairs of the electrical connection points on the electronic device and the specific mounting location on the substrate surface.

Abstract: An InGaN-based resonant cavity enhanced detector chip based on porous DBR, including: a substrate (10); a buffer layer (11) formed on the substrate (10); a bottom porous DBR layer (12) formed on the buffer layer (11); an n-type GaN layer (13) formed on the bottom porous DBR layer (12), wherein one side of the n-type GaN layer (13) is recessed downward to form a mesa (13?), and the other side of the n-type GaN layer (13) is protruded; an active region (14) formed on the n-type GaN layer (13); a p-type GaN layer (15) formed on the active region (14); a sidewall passivation layer (20) formed on an upper surface of the p-type GaN layer (15) and sidewalls of the protruded n-type GaN layer (13), the active region (14), and the p-type GaN layer (15), wherein the sidewall passivation layer (20) on the upper surface of the p-type GaN layer (15) has a window in a middle; a transparent conductive layer (16) formed on the sidewall passivation layer (20) and the p-type GaN layer (15) at the window; an n-type electrode (18

Abstract: A method of forming a semiconductor device comprises patterning a mask material adjacent to an array of transistors, forming an electrically conductive material between adjacent portions of the patterned mask material, forming an additional mask material over the patterned mask material to form a mask structure, the additional mask material having an arcuate cross-sectional shape, removing a portion of the additional mask material to reduce a spacing between adjacent portions of the additional mask material, and forming capacitor structures in openings between the mask structure. Additional methods of forming a semiconductor device, and related semiconductor devices and related systems are also disclosed.

Abstract: A dynamic random access memory (DRAM) and a method of fabricating the same are provided. The DRAM includes a substrate, a plurality of first isolation structures, a plurality of word line structures, a plurality of second isolation structures, and a plurality of third isolation structures. The plurality of first isolation structures are located in the substrate to define a plurality of active areas arranged along a first direction, wherein the plurality of active areas and the plurality of first isolation structures are alternately arranged along the first direction. The plurality of word line structures pass through the plurality of active areas and the plurality of first isolation structures. The plurality of word line structures are arranged along a second direction and extended along a third direction.

Abstract: Described herein is an integrated circuit device comprising a conductive line structure including a bit line and an insulating capping pattern; and an insulating spacer covering a side wall of the conductive line structure, the insulating spacer including an inner spacer and a char spacer. To form the insulating spacer, a polymer brush pattern may be chemically bonded to the inner spacer to cover a side wall of the conductive line structure; a first insulating spacer film covering the inner spacer and the polymer brush pattern may be formed; and a char spacer may be formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen.

Abstract: A photoelectric conversion apparatus includes a semiconductor layer including a photoelectric conversion portion, a charge holding portion configured to hold electric charge generated from the photoelectric conversion portion, and a charge detection portion to which the electric charge held by the charge holding portion is transferred. A gate electrode of a transistor and a light shielding film including a first portion covering the charge holding portion and a second portion covering an upper surface of the gate electrode are disposed above the semiconductor layer. The distance between the second portion of the light shielding film and the upper surface of the gate electrode is greater than the distance between the first portion of the light shielding film and the semiconductor layer.

Abstract: A semiconductor package includes a semiconductor die and a bridge die. The bridge die includes through vias, and the through vias are connected to post bumps. The through vias are electrically connected to the semiconductor die by redistribution lines.

Abstract: A magnetic memory device includes a first dielectric layer on a substrate, first and second via plugs in the first dielectric layer, first and second cylindrical memory stacks on the first and second via plugs, respectively, and an insulating cap layer conformally disposed on the first dielectric layer and on sidewalls of the first and second cylindrical memory stacks. The insulating cap layer is not disposed in a logic area and a via forming region between the first and second cylindrical memory stacks.

Abstract: A semiconductor package includes first and second semiconductor dies, first and second redistributed line structures, a first bridge die, and a vertical connector. The first semiconductor die and the first bridge die are disposed on the first redistributed line structure. The first bridge die is disposed to provide a level difference between the first semiconductor die and the first bridge die, the first bridge die having a height that is less than a height of the first semiconductor die. The second redistributed line structure has a protrusion, laterally protruding from a side surface of the first semiconductor die when viewed from a plan view, and a bottom surface of the second redistributed line structure is in contact with a top surface of the first semiconductor die. The second semiconductor die is disposed on the second redistributed line structure. The vertical connector is disposed between the bridge die and the protrusion of the second redistributed line structure to support the protrusion.

Abstract: An image sensor may include a photoelectric device configured to selectively absorb light associated with a first color of three primary colors, a semiconductor substrate that is stacked with the photoelectric device and includes first and second photo-sensing devices configured to sense light associated with second and third colors of three primary colors. The first and second photo-sensing devices may have different thicknesses, different depths from a surface of the semiconductor substrate, or different thicknesses and different depths from the surface of the semiconductor substrate. At least one part of a thickness area of the first photo-sensing device may overlap at least one part of a thickness area of the second photo-sensing device in a parallel direction extending substantially parallel to the surface of the semiconductor substrate.

Abstract: Embodiments described in this disclosure relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In some examples, after an interfacial layer and a gate dielectric layer are deposited, a rapid anneal process, such as laser anneal or flash lamp anneal process, is performed in a controlled ambient nitrogen-containing environment to form a nitrided portion in the gate dielectric layer. The nitrided portion passivates the defects at the surface of the gate dielectric layer and can serve as a barrier to prevent etchant chemistry and defects/dopants from the subsequent gate stack layers from affecting or diffusing through the gate dielectric layer. Particularly, the rapid anneal process is performed on a millisecond scale to confine nitrogen atoms in the gate dielectric layer without diffusing into the underlying interfacial dielectric and/or any neighboring structure such as fin.