Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.

Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

Abstract: A method and apparatus for light induced selective transfer of components. A donor substrate (10) with a plurality of components (11,12) divided in different subsets arranged according to respective layouts (A,B). A target substrate (20) comprises recesses (21) and protrusions (25). The donor and target substrates (10,20) are aligned such that a first subset of components (11) is suspended over corresponding recesses (21) in the target substrate (20) and a second subset of components (12) is in contact with corresponding protrusions (25) of the target substrate (20). Light (L) is projected onto the donor substrate (10) to transfer the first subset of components (11) across and into the corresponding recesses (21) while the second subset of components (12) remains attached to the donor substrate (10).

Abstract: An imaging element includes a photoelectric conversion unit including a first electrode, a photoelectric conversion layer, and a second electrode that are stacked, in which an inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer, and the inorganic oxide semiconductor material layer includes at least two types of elements selected from the group consisting of indium, tungsten, tin, and zinc. Alternatively, a LUMO value E1 of a material included in a part of the photoelectric conversion layer positioned near the inorganic oxide semiconductor material layer and a LUMO value E2 of a material included in the inorganic oxide semiconductor material layer satisfy E1-E2<0.2 eV. Alternatively, the mobility of a material included in the inorganic oxide semiconductor material layer is equal to or greater than 10 cm2/V·s.

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

Abstract: An LED assembly includes an LED light source having a first light output with a characteristic spectrum, and a yellow-green phosphor, red phosphor, and neodymium fluorine absorber combination through which the first light output passes, wherein the yellow-green phosphor, red phosphor, and neodymium fluorine absorber combination is configured to convert the first light output to a second light output having a predetermined correlated color temperature.

Abstract: The invention discloses a packaging structure and manufacturing method of a SiC MOSFET module, which is composed of SiC MOSFET chips, upper DBC substrate, lower DBC substrate, ceramic interposer, silicon oxide dielectric layer, nano silver pastes, redistribution layer, through-ceramic-hole conductive metals and power terminals. The SiC MOSFET chips are connected to the lower DBC substrate using nano silver pastes in the invention. Besides, some rectangular frames are made on the ceramic interposer, and the SiC MOSFET chips are embedded in the ceramic interposer by filling dielectric materials. The upper surfaces of the chips and the ceramic interposer are covered with a conductive metal redistribution layer, and the upper and lower surfaces of the ceramic interposer are interconnected with the upper and lower DBC substrates, respectively. The power terminals are led out from the conductive copper layers of the upper and lower DBC substrates.

Abstract: A semiconductor package including a lower redistribution layer including wiring patterns; a lower substrate on the lower redistribution layer, the lower substrate including a cavity; an application processor on the lower redistribution layer in the cavity; a cache memory chip on the application processor; a passive device module on the application processor; a plurality of first through-silicon vias penetrating the application processor to connect the lower redistribution layer to the passive device module; and lower bumps on a bottom surface of the lower redistribution layer, wherein the passive device module is adjacent to a side of the cache memory chip.

Abstract: A method and a transistor device are disclosed. The method includes: forming a trench in a first surface in an edge region of a semiconductor body; forming an insulation layer in the trench and on the first surface of the semiconductor body; and planarizing the insulation layer so that a trench insulation layer that fills the trench remains, wherein forming the insulation layer comprises a thermal oxidation process.

Abstract: A method of forming an air-gap spacer in a semiconductor device includes providing a device including a gate stack, a plurality of spacer layers disposed on a sidewall of the gate stack, and a source/drain feature adjacent to the gate stack. In some embodiments, a first spacer layer of the plurality of spacer layers is removed to form an air gap on the sidewall of the gate stack. In various examples, a first sealing layer is then deposited over a top portion of the air gap to form a sealed air gap, and a second sealing layer is deposited over the first sealing layer. Thereafter, a first self-aligned contact (SAC) layer is etched from over the source/drain feature using a first etching process. In various embodiments, the first etching process selectively etches the first SAC layer while the first and second sealing layers remain unetched.

Abstract: Embodiments of the present disclosure relate to a transistor and methods for forming a transistor. A transistor includes a gate electrode structure disposed over a channel region, a source/drain extension region disposed adjacent to the channel region, and a source/drain region disposed on the source/drain extension region. The source/drain region includes antimony (Sb). The method of forming a transistor includes forming the source/drain extension region and forming the source/drain region on the source/drain extension region. The antimony helps prevent unwanted migration of dopants from the source/drain region to the source/drain extension region.

Abstract: A display device that can reduce power consumption is provided. The display device can include a substrate provided with a first subpixel and a second subpixel, a first electrode provided on the substrate, a first light emitting layer provided on the first electrode and emitting light of a first color, a second electrode provided on the first light emitting layer, a second light emitting layer provided on the second electrode and emitting light of a second color, and a third electrode provided on the second light emitting layer. The second electrode is disconnected between the first subpixel and the second subpixel, and the second electrode of the first subpixel is electrically connected with the third electrode.

Abstract: Techniques and mechanisms for bonding structures of a circuit device with a monolayer. In an embodiment, a patterned metallization layer or a first dielectric layer includes a first surface portion. The first surface portion is exposed to first molecules which each include a first head group and a first end group which is substantially non-reactive with the first head group. The first head groups attach to the first portion to form a first self-assembled monolayer, which is subsequently reacted with second molecules to form a second monolayer comprising moieties of the first molecules. In another embodiment, the first head group comprises a first moiety comprising a sulfur atom or a nitrogen atom, where the first end group comprises one of an acid moiety, an acid anhydride moiety, an aliphatic alcohol moiety, an aromatic alcohol moiety, or an unsaturated hydrocarbon moiety.

Abstract: A three-dimensional flash memory device is described that may include a substrate, a plurality of cell gate patterns and a plurality of mold insulating layers alternately stacked on the substrate, and a vertical channel structure in contact with side surfaces of the plurality of cell gate patterns and side surfaces of the plurality of mold insulating layers. Each of the plurality of cell gate patterns may include a cell gate electrode and a blocking barrier pattern adjacently disposed on one side surface of the cell gate electrode. An inner side surface of the blocking barrier pattern may include an upper inner side surface, a middle inner side surface, and a lower inner side surface. The middle inner side surface of the blocking barrier pattern may face the one side surface of the cell gate electrode.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has an image sensor within a substrate. A first dielectric has an upper surface that extends over a first side of the substrate and over one or more trenches within the first side of the substrate. The one or more trenches laterally surround the image sensor. An internal reflection structure arranged over the upper surface of the first dielectric. The internal reflection structure is configured to reflect radiation exiting from the substrate back into the substrate.

Abstract: An integrated circuit structure includes: a first plurality of cell rows extending in a first direction, each of which has a first row height and comprises a plurality of first cells disposed therein; and a second plurality of cell rows extending in the first direction, each of which has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction, and wherein the plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction.

Abstract: A semiconductor component includes a SiC semiconductor body having an active region and an edge termination structure at least partly surrounding the active region. A drift zone of a first conductivity type is formed in the SiC semiconductor body. The edge termination structure includes: a first doped region of a second conductivity type between a first surface of the SiC semiconductor body and the drift zone, the first doped region at least partly surrounding the active region and being spaced apart from the first surface; a plurality of second doped regions of the second conductivity type between the first surface and the first doped region; and third doped regions of the first conductivity type separating adjacent second doped regions of the plurality of second doped regions from one another in a lateral direction.

Abstract: A manufacturing method of a semiconductor module including a trimming resistance element and a plurality of transistor chips connected mutually in parallel, in which gate electrodes are connected to one end of the trimming resistance element, including: measuring elapsed time and a gate-source voltage value when a predetermined gate current is injected into the gate electrodes and a predetermined drain current flow; calculating a gate-source capacity on the basis of the gate-source voltage value; determining a compensation gate resistance value on the basis of the gate-source voltage value and the gate-source capacity; and changing a resistance value of the trimming resistance element such that the resistance value of the trimming resistance element is conformed to the compensation gate resistance value.

Abstract: The disclosed apparatus may include (1) a split heatsink assembly that comprises (A) a first heatsink that includes a base for thermally coupling to a first heat-emitting component, wherein the base of the first heatsink forms an opening, and (B) a second heatsink that includes a pedestal for thermally coupling to a second heat-emitting component, wherein the pedestal of the second heatsink fits into the opening formed by the base of the first heatsink, and (2) an EMI absorber that at least partially encompasses the pedestal of the second heatsink and resides between the pedestal of the second heatsink and the base of the first heatsink in the opening. Various other apparatuses, systems, and methods are also disclosed.