Abstract: A semiconductor component includes a SiC semiconductor body having an active region and an edge termination structure at least partly surrounding the active region. A drift zone of a first conductivity type is formed in the SiC semiconductor body. The edge termination structure includes: a first doped region of a second conductivity type between a first surface of the SiC semiconductor body and the drift zone, the first doped region at least partly surrounding the active region and being spaced apart from the first surface; a plurality of second doped regions of the second conductivity type between the first surface and the first doped region; and third doped regions of the first conductivity type separating adjacent second doped regions of the plurality of second doped regions from one another in a lateral direction.

Abstract: A manufacturing method of a semiconductor module including a trimming resistance element and a plurality of transistor chips connected mutually in parallel, in which gate electrodes are connected to one end of the trimming resistance element, including: measuring elapsed time and a gate-source voltage value when a predetermined gate current is injected into the gate electrodes and a predetermined drain current flow; calculating a gate-source capacity on the basis of the gate-source voltage value; determining a compensation gate resistance value on the basis of the gate-source voltage value and the gate-source capacity; and changing a resistance value of the trimming resistance element such that the resistance value of the trimming resistance element is conformed to the compensation gate resistance value.

Abstract: The disclosed apparatus may include (1) a split heatsink assembly that comprises (A) a first heatsink that includes a base for thermally coupling to a first heat-emitting component, wherein the base of the first heatsink forms an opening, and (B) a second heatsink that includes a pedestal for thermally coupling to a second heat-emitting component, wherein the pedestal of the second heatsink fits into the opening formed by the base of the first heatsink, and (2) an EMI absorber that at least partially encompasses the pedestal of the second heatsink and resides between the pedestal of the second heatsink and the base of the first heatsink in the opening. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A device includes a die with perimeters associated therewith, a substrate, and a test channel. The die is coupled to the substrate via a plurality of C4 bumps on a first side of the substrate. The substrate has connections on a second side of the substrate, opposite to the first side. A first connection connects a C4 bump on the first side of the substrate to a connection on the second side using a metal layer. The test channel is positioned within the substrate and further positioned outside of the perimeter of the die coupled to the substrate. The test channel is positioned at substantially a same depth as the metal layer of the first connection. A probe connecting to the test channel via pads positioned on a same side of the substrate that provides electrical characteristics that is substantially the same as electrical characteristics of the first connection.

Abstract: Embodiments described herein generally relate to an electronics assembly that includes a semiconductor device, a substrate layer, a first mesh layer and a second mesh layer. Jet channels that have a first inner diameter are disposed within the substrate layer. The first mesh layer includes a first plurality of pores that have a perimeter opening. The second mesh layer includes a second plurality of pores that have a second inner diameter. The jet channels, the first and the second plurality of pores are concentric to create a fluid path for a fluid to impinge a first device surface of the semiconductor device. The second inner diameter is smaller than the perimeter opening and the first inner diameter of the substrate layer such that a cooling fluid velocity increases when flowing from the substrate layer through the second mesh layer.

Abstract: In one example, a semiconductor device structure relates to an electronic device, which includes a device top surface, a device bottom surface opposite to the device top surface, device side surfaces extending between the device top surface and the device bottom surface, and pads disposed over the device top surface. Interconnects are connected to the pads, and the interconnects first regions that each extend from a respective pad in in an upward direction, and second regions each connected to a respective first region, wherein each second region extends from the respective first region in a lateral direction. The interconnects comprise a redistribution pattern on the pads. Other examples and related methods are also disclosed herein.

Abstract: The present disclosure provides a current-driven display, including a substrate and a first electrode layer stacked on the substrate in a stacking direction. The substrate includes a plurality of light-emitting units and a spacer separating each of the plurality of light-emitting units from one another. The first electrode layer includes a first region and a second region. The first region and the second region contact one of the plurality of light-emitting units, respectively, and are separated by the spacer. The current-driven display further includes a second electrode layer, which equipotentially connects the first region and the second region across the spacer. The present disclosure also provides a method for producing a current-driven display.

Abstract: A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure. The multi-layer stacked structure includes a stair region and an non-stair region, the stair region includes a plurality of steps, each step includes an immediately-adjacent pair of the conductive layers and insulating layers. A plurality of memory structures are located in the non-stair region, and each memory structure passes through the conductive layers and the insulating layers. A fishbone dielectric structure includes a main bone and a plurality of side bones extending from the main bone in the stair region, wherein the main bone crosses the memory structures in the non-stair region.

Abstract: Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM).

Abstract: One illustrative method disclosed herein includes, among other things, selectively forming a sacrificial material on an upper surface of a top electrode of a memory cell, forming at least one layer of insulating material around the sacrificial material and removing the sacrificial material so as to form an opening in the at least one layer of insulating material, wherein the opening exposes the upper surface of the top electrode. The method also includes forming an internal sidewall spacer within the opening in the at least one layer of insulating material and forming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein a portion of the conductive contact structure is surrounded by the internal sidewall spacer.

Abstract: A display device includes a first electrode, a pixel define layer disposed on the first electrode, the pixel define layer including an opening, an organic emission layer disposed on the pixel define layer, the organic emission layer in electrical communication with the first electrode through the opening, a second electrode disposed on the organic emission layer, a light recycle layer disposed on the second electrode, and a color filter layer disposed on the light recycle layer, the color filter layer including a quantum dot, wherein a width of the organic emission layer is longer than a width of the color filter layer.

Abstract: A magnetoresistance effect element includes a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer that is interposed between the first ferromagnetic layer and the second ferromagnetic layer. The tunnel barrier layer is a stacked body including one or more high-barrier-height layers and one or more low-barrier-height layers, the one or more high-barrier-height layers having a relatively high barrier height with respect to the one or more low-barrier-height layers and the one or more low-barrier-height layers having a relatively low barrier height with respect to the one or more high-barrier-height layers. A minimum difference of barrier height between the one or more high-barrier-height layers and the one or more low-barrier-height layers is equal to or higher than 0.5 eV.

Abstract: A display device according to an exemplary embodiment includes a display panel including a display area and a bending region. The display panel in the bending region includes a plurality of connection wires, a pattern including a plurality of electrodes, and a protection layer positioned between the plurality of connection wires and the pattern.

Abstract: An organic light-emitting display device including a substrate on which a plurality of sub-pixels are arranged; a thin film transistor and a first electrode of an organic light-emitting diode connected to the thin film transistor, the thin film transistor and the organic light-emitting diode being disposed in each of the plurality of sub-pixels; a first bank layer disposed on the first electrode and exposing the first electrode; and a second bank layer disposed on the first bank layer and exposing the first bank layer and the first electrode. Further, the first bank layer includes first regions overlapping with via holes through which the thin film transistor is connected to the first electrode and second regions which are regions other than the first regions, and a thickness of the first regions is greater than a thickness of the second regions.

Abstract: An electroluminescent display device comprises a substrate; a thin film transistor disposed on the substrate; an overcoat layer disposed on the thin film transistor; and a light-emitting diode electrically connected to the thin film transistor through the overcoat layer, wherein the light-emitting diode includes a first electrode, a light-emitting layer on the first electrode and a second electrode on the light-emitting layer, and an emissive area is an area in which the light-emitting layer emits light by the first electrode or the second electrode, wherein the overcoat layer includes a micro lens at a position corresponding to the emissive area, and the light-emitting diode conforms to a morphology of the micro lens, and wherein the first electrode includes a first region and a second region, the first region comprises an electrode layer, and the second region includes the electrode layer and an electrode pattern disposed under the electrode layer.

Abstract: A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die.

Abstract: Device structures are provided that include one or more plasmonic OLEDs and zero or more non-plasmonic OLEDs. Each plasmonic OLED includes an enhancement layer that includes a plasmonic material which exhibits surface plasmon resonance that non-radiatively couples to an organic emissive material and transfers excited state energy from the emissive material to a non-radiative mode of surface plasmon polaritons in the plasmonic OLED.

Abstract: A photoelectric conversion element according to an embodiment of the present disclosure includes: a first electrode and a second electrode facing each other; and a photoelectric conversion layer provided between the first electrode and the second electrode, and including a first organic semiconductor material, a second organic semiconductor material, and a third organic semiconductor material that have mother skeletons different from one another. The first organic semiconductor material is one of fullerenes and fullerene derivatives. The second organic semiconductor material in a form of a single-layer film has a higher linear absorption coefficient of a maximal light absorption wavelength in a visible light region than a single-layer film of the first organic semiconductor material and a single-layer film of the third organic semiconductor material. The third organic semiconductor material has a value equal to or higher than a HOMO level of the second organic semiconductor material.

Abstract: An electroluminescent display device includes a substrate; an overcoat layer disposed over the substrate; and a light-emitting diode disposed on the overcoat layer, comprising: a first electrode having a plurality of holes exposing a top surface of the overcoat layer, the holes having an inclined wall surface; a light-emitting layer disposed on the first electrode; and a second electrode disposed on the light-emitting layer.

Abstract: A semiconductor power device and a manufacturing method thereof are provided. In the manufacturing method, before the self-aligned silicide process is performed, a gate stacked structure and a spacer are formed on a semiconductor layer having a body region and a source region. The spacer defines a portion of the source region for forming a silicide layer. Subsequently, the self-aligned silicide process is performed with the gate stacked structure and the spacer functioning as a mask to form the silicide layer at the defined portion of the source region. Thereafter, an interconnection structure including an interlayer dielectric layer and a source conductive layer is formed on the semiconductor layer. The source conductive layer is electrically connected to the source region. The silicide layer extends toward the gate stacked structure from a position under the source conductive layer to another position under the interlayer dielectric layer.