Abstract: An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. It is a preferred method of the invention to perform the deposition at a temperature of about 750-850.degree. C. and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface.

Abstract: Method of fabricating semiconductor devices comprising the steps of: mounting a plurality of semiconductor chips on a film carrier tape; sealing each one of the semiconductor chips mounted on the film carrier type with epoxy resin; attaching an individual stiffener to the film carrier tape at a position corresponding to each one of the semiconductor chips; forming a plurality of bumps on the film carrier tape at a position corresponding to each one of the semiconductor chips; and punching out the film carrier tape into separate pieces of insulating film after above-described steps. In this method, each step is carried out on the film carrier tape running between supply and take-up reels.

Abstract: A semiconductor processing method of reducing thickness depletion of a nitride layer at a junction of different underlying layers includes, a) providing a substrate, the substrate comprising a first material and a second material, the first and second materials joining at a surface junction, the first and second materials being different from one another; b) exposing the substrate to a nitrogen containing gas under pressure and elevated temperature conditions effective to nitridize an outer portion of both the first and second materials with the nitrogen containing gas to provide a nitrogen containing nucleation layer at the outer portion of both of the first and second materials over the surface junction; and c) chemical vapor depositing a nitride layer atop the nucleation layer over the first and second materials and the surface junction.

Abstract: A method of removing metallic impurities diffused in a semiconductor substrate, comprising, the semiconductor-substrate-heating step of heating a semiconductor substrate to at least 200.degree. C. or higher and promoting the release and rediffusion of metallic impurities diffused in the semiconductor substrate, and the metallic-impurity-removing step of dissolving the metallic impurities arrived at the surface of the semiconductor substrate with a chemical agent and removing them from the substrate.

Abstract: Disclosed is a method of manufacturing a semiconductor device, comprising the step of detachably mounting a plurality of semiconductor substrates to a first holder board so as to form a complex semiconductor substrate, and the step of subjecting the plural semiconductor substrates included in the complex semiconductor substrates to common steps of manufacturing a semiconductor device. At least one of the plural semiconductor substrates is mounted to a second holder board. The particular semiconductor substrate is detached from the second holder board and, then, mounted to the first holder board. Alternatively, at least one of the plural semiconductor substrates is detached from the first holder board and, then, mounted to a third holder board differing in size from the first holder board.

Abstract: A method and a device for bonding a first plate-shaped object to a second plate-shaped object with an adhesive. The adhesive is applied to one of the two surfaces of the first object, whereafter said surface of the first object and one of the two surfaces of the second object are pressed together. The plate-shaped objects are rotated at equal rotational velocities about an axis of rotation extending perpendicularly to said surfaces of the objects for at least a time period during which the two objects are being pressed together. In this way, the adhesive present between the two objects spreads homogeneously between the two objects under the influence of the centrifugal force acting on the adhesive, so that a homogeneous, relatively thin and strong layer of adhesive is formed between the two objects. In addition, the pressure with which the objects are to be pressed together is reduced.

Abstract: A method for fabricating a BGA package is provided. The method includes the step of providing a substrate having a first surface with a pattern of conductors thereon, and an opposing second surface with a die attach area thereon. A first solder mask is formed on the first surface with via openings to ball bonding pads on the conductors. A second solder mask is formed on the second surface with an opening on the die attach area. The opening in the second solder mask permits a die to be placed through the opening and adhesively bonded directly to the substrate. The die can then be wire bonded to the conductors and encapsulated in an encapsulating resin. In addition solder balls can be placed in the via openings and bonded to the ball bonding pads.

Abstract: A lead frame comprises an island supported by island supports at its four corners and leads extending from its frame section to the island. The leads are composed of inner leads and outer leads which are connected to each other with dam bars. Plating layers are formed on the surfaces of the tip sections of the inner leads, and lead-fixing tape is bonded to the distal portions of the inner leads with an adhesive which acquires elastic properties when set. The lead-fixing tape is bonded with its inner side located 0.1 mm-2 mm inward from the tips of the inner leads.

Abstract: A method for producing a noble metal-containing structure on a substrate, and a semiconductor component having such a noble metal-containing structure, include introducing a noble metal into a preliminary structure by converting a gaseous compound of the noble metal with a non-noble metal in a preliminary structure into elementary noble metal and a gaseous compound of the non-noble metal. The process continues until a desired amount of the non-noble metal in the preliminary structure is replaced by the noble metal.

Abstract: A semiconductor structure includes a stack of two semiconductor chips. An edge of the chips forms a side surface of the stack. Insulation and adhesive is located between the chips, and a wire contacting circuitry on one of the chips extends through the insulation to the side surface. A first conductor contacts the wire on the side surface. The first conductor is self-aligned to the wire and extends above the side surface. The first conductor facilitates pads or connectors on the side surface that are insulated from the semiconductor chips. The self-aligned first conductor is an electroplated or electroless plated metal.

Abstract: A silicon oxide film is used as a mask covering an amorphous silicon film. A film having a catalyst element such as nickel for promoting crystallization is formed. When heat annealing is applied, the catalyst element diffuses from the aperture into the amorphous silicon film to obtain a crystalline silicon film. The silicon film has uniformly orientated crystals. Then, a halogen-containing gas (for example, hydrogen chloride) is introduced while the mask in place. In this step, the atmosphere and the temperature are controlled to form, on the silicon film in the portion of the aperture, an oxide film of such a thickness as allowing the catalyst element to pass but not etching the silicon film. The catalyst element in the silicon film is removed by halogen through the aperture, but the crystallinity of silicon does not change. Thus, a silicon film of good crystallinity can be obtained.

Abstract: The present invention provides a method of forming gate side wall insulation films on side walls of a gate electrode on a gate insulation film over a silicon substrate surface. The method comprises The following steps. Gate side wall insulation films are selectively formed on side walls of a gate electrode. A silicon film is selectively grown on at least any one of a top of the gate electrode and on the silicon substrate surface. Surface regions of the gate side wall insulation films are etched.

Abstract: A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.

Abstract: Silver-tin alloy solder bumps are fabricated by forming a masked underbump metallurgy layer on a microelectronic substrate, to define exposed portions of the underbump metallurgy layer, plating silver on the exposed portions of the underbump metallurgy, plating tin on the silver and reflowing to form silver-tin alloy solder bumps. Accordingly, silver-tin alloy is not plated. Rather, individual layers of silver and tin are plated, and then reflowed to form silver-tin alloy solder bumps.

Abstract: A method is provided involving re-slicing a wafer after dual-side alignment and processing has been performed. This procedure provides twice as many processed electronic devices without increasing the number of loading, processing and unloading procedures performed or the total number of substrates used. Another method is provided for creating two processed chips by attaching two conventional substrates, processing IC's on each of the two exposed, polished sides and then detaching the substrates. This technique reduces the number of loading, processing and unloading procedures required to produce a given number of IC chips by half. An apparatus and further method provides two different subsystems of a single IC processed on opposite sides of the same chip. Such a device saves cost by using fewer substrates to make the same number of chips. Also, the method performs loading, processing and unloading procedures half as much to produce a given number of IC's.

Abstract: The present invention includes integrated circuit devices, synchronous-link dynamic random access memory devices, methods of forming an integrated circuit device and methods of forming a synchronous-link dynamic random access memory edge-mounted device. According to one aspect of the present invention, an integrated circuit device includes a semiconductor die and a first housing encapsulating the semiconductor die. A heat sink is positioned proximate the first housing and a second housing is formed to encapsulate at least a portion of the heat sink. The heat sink is preferably thermally coupled with the semiconductor die and configured to expel heat therefrom. Another aspect provides a method of forming an integrated circuit device including the steps of providing a semiconductor die; forming a first housing about the semiconductor die; thermally coupling a heat sink with the first housing; and forming a second housing about at least a portion of the heat sink following the thermally coupling.

Abstract: A chemical mechanical polishing process in a wafer is polished with slurry under selected operating conditions for a first time period that avoids overpolishing; and then polished with DI water under the selected operating conditions for a second time period until the surface of the wafer is substantially planar and dishing is minimized. The process can be used in conjunction with a damascene or dual-damascene process in which tungsten is polished with respect to BPSG.

Abstract: A production method for forming contact structures on a planar surface of a substrate.

Abstract: An integrated circuit package with heat slug is disclosed. The heat slug is thermally coupled to one or more semiconductor die using a single layer of high conductivity adhesive. The assembly process of this invention includes the steps of initially attaching a temporary heat slug to the back side of a package body, to which one or more semiconductor die are attached. The semiconductor die are then electrically connected to the package body and encapsulated to maintain fixed positions within the package cavity. The temporary heat slug is then moved and a final heat slug is attached to the package body and the back side of the one or more semiconductor dies utilizing a single layer of high conductivity adhesive. The package is compact, has reduced complexity, and is inexpensive to manufacture.

Abstract: A method of preventing edge stain in silicon wafers from the edge polishing step with an alkaline slurry, the method consisting of formation of an oxide layer by an ozone dipping step prior to edge polishing.