Abstract: An integrated circuit package. The package includes a substrate which has a first surface, a second opposite surface and four corners. Each corner has a conductive plane and at least one via. The vias connect the conductive planes of the first surface with corresponding conductive planes located on the second surface of the substrate. An integrated circuit is mounted to the first surface of the substrate and enclosed by plastic. Solder balls are attached to the conductive planes and a number of individual solder pads located on the second surface of the package. The contacts are connected to a printed circuit board. A lid is attached to the conductive planes at the four corners of the substrate. Some of the heat generated by the integrated circuit conducts through the substrate and into the printed circuit board. Some of the heat within the substrate conducts into the lid through the conductive planes located at the corners of the package.

Abstract: An interconnect for semiconductor components such as dice, wafers and chip scale packages is provided. The interconnect includes a substrate, and patterns of contacts formed on a face side of the substrate adapted to electrically engage external contacts (e.g., bond pads, solder bumps) on the components. The interconnect also includes insulated conductive members through the substrate, which provide direct electrical paths from the interconnect contacts to a backside of the substrate. The conductive members can be formed by laser machining openings in the substrate, and then filling the openings with a conductive material (e.g., metal, conductive polymer). The conductive members can also include pads with contact balls, configured for electrical interface with a test apparatus, such as test carrier or wafer handler. The interconnect can be used to construct test systems for testing semiconductor components, or to construct chip scale packages and multi chip modules.

Abstract: A semiconductor chip packaging method includes the provision of individual elastomer chip carriers cut from an elastomer sheet having a uniform thickness and smooth, parallel surfaces. The elastomer sheet is mounted on an adhesive tape held by a fixing member, such as a support ring, and is then divided into individual carriers. The carrier is attached to a circuit interposer, and a semiconductor chip is attached to the carrier. Circuit leads of the interposer are bonded to connection pads on the chip. The beam lead bonding area is then encapsulated, and conductive bumps are formed on the underside of the package to serve as input/output terminals for the packaged device. Using this method, an number of devices can be packaged simultaneously on a flexible sheet and then separated into individual devices by cutting the sheet between the devices.

Abstract: The present invention provides a method of making CSP type semiconductor devices by the use of an general-purpose gang bonding type bonder while improving the yield. The method includes the steps of forming an imitation film carrier tape (20), disposing the imitation film carrier tape (20) relative to a semiconductor chip (12) so that an imitation junction (26a) and an electrode (13) face in a direction of opposing each other, positioning the imitation junctions (26a) with the electrode (13) while being observed through an aperture (22), removing the imitation film carrier tape (20) from the semiconductor chip and disposing a film carrier tape (30) at the same position as occupied by the imitation film carrier tape (20).

Abstract: A method of eliminating an edge effect in chemical vapor deposition of a metal such as copper on a semiconductor substrate surface. A susceptor in a reaction chamber is exposed to a plasma. A substrate contained thereon and processed by chemical vapor deposition has a uniform metal layer at edge and non-edge surfaces. A plurality of substrates may be processed before reexposing the susceptor to the plasma.

Abstract: A method of making a semiconductor package comprises applying a coating layer to a degating region of a substrate on which a runner and a gate of an encapsulating mold are located, allowing the adhesion between the coating layer and the surface of the substrate to be less than that between the coating layer and a molding compound subsequently molded over the coating layer. A semiconductor chip is then attached to the substrate followed by a cleaning treatment to the surfaces of the substrate and semiconductor chip. The semiconductor chip is then electrically connected to the substrate by wire bonding. After that, the molding compound is transfer molded to enclose the semiconductor chip and part of the surface of the substrate. The molding compound solidified and formed in the runner and gate of the encapsulating mold is then removed from the substrate by breaking away, together with the coating layer adhered thereto.

Abstract: When a semiconductor chip is mounted on a circuit substrate, the space therebetween can be briefly sealed with a resin encapsulant by transfer molding an encapsulating resin composition in molten state and under pressure into the space and heat curing the composition thereat. The composition contains (a) an epoxy resin, (b) a curing agent, and (c) an inorganic filler having a maximum particle size of up to 24 .mu.m and has a melt viscosity of up to 200 poises at the molding temperature. Then encapsulation can be completed within a very short cycle without allowing the filler to settle. Semiconductor devices are manufactured to high reliability.

Abstract: A thermoelectric piece has an increased adhesive strength between a semiconductor matrix of Bi--Sb--Te or Bi--Te--Se and a diffusion barrier layer deposited thereon for blocking diffusion of a soldering material into the semiconductor matrix. An Sn-alloy layer is provided between the semiconductor matrix and the diffusion barrier layer of Mo, W, Nb and Ni to give the enhanced adhesive strength. The Sn-alloy is formed at the interface with the semiconductor matrix by interdiffusion of Sn with at least one element of the semiconductor. It is found that Sn will not lower the thermoelectric characteristics when diffusing into the semiconductor matrix and provides an sufficient adhesive strength to the metal elements of the diffusion barrier layer.

Abstract: A memory cell is formed including an insulation region on the substrate and a transistor including a gate on the substrate and a source/drain region in the substrate disposed between the gate and the insulation region. The cell also includes a capacitor including an electrode overlying the insulation region, the electrode having a lateral surface adjacent the source/drain region. A conductive interconnecting region is formed on the substrate and extends from the source/drain region to contact the lateral surface of the first electrode of the capacitor. The capacitor may include a first electrode on the insulation region, a dielectric region on the first electrode, and a second electrode on the dielectric region. The first electrode preferably is platinum and the dielectric region preferably is a ferroelectric material such as lead zirconate titanate (PZT) or Ba.sub.x Sr.sub.1-x TiO.sub.3 (BST).

Abstract: A method for reducing the formation of watermarks includes providing a semiconductor wafer and contacting the semiconductor wafer with a solution containing a watermark reducing amount of at least one cationic surfactant.

Abstract: A technique for enabling sufficient flow of flux cleaning fluids and an underfill material in the relatively low-profile gap between a flip-chip bonded IC chip and a substrate, such as a printed circuit board, is to provide at least one aperture in the substrate under the IC chip. The use of such an aperture enables, for example, flux cleaning fluid to flow through the aperture into the low-profile gap between the IC chip and the substrate surface, such as by the application of pressure or by gravity, which then exits through openings between formed interconnect bonds at a sufficient flow rate to adequately remove flux residues. An epoxy underfill to the IC chip can be formed in a similar manner. For example, a relatively thick bead of epoxy, such as on the order of the thickness of the IC chip, is deposited or stencil printed on the substrate surface around the edges of the IC chip and capillary action is then relied upon to draw the epoxy into the low-profile gap.

Abstract: A method for fabricating a printed-circuit board includes the steps of loading components onto the printed circuit board, and placing a pin array over the components. Each pin is free to move "downward," and each component has at least one pin pressing on it to hold the component in place. Each component also preferably has a pin on each side of it, to hold it against lateral movement. The pin support arrangement is dimensioned so that a gap or space exists between the support and the component side of the board. Heat is applied to the gap, and flows through the interstices between the pins to heat the solder on the upper side of the board to fuse the solder and make the desired connections.

Abstract: A method of forming a bonding pad is provided. A substrate is provided and a multi-metal layer is formed on the substrate. An inter-metal dielectric layer with a trench is formed on the multi-metal layer. A conformal barrier layer is formed on the inter-metal dielectric layer. A first metal layer is formed on the barrier layer to fill a part of the trench. A second metal layer is formed on the first metal layer to fill the trench. A part of the first metal layer and a part of the second metal layer flowing out the trench are removed to expose the inter-metal dielectric layer. A cap layer is formed on the inter-metal dielectric layer. A passivation layer is formed on the cap layer. A part of the passivation and a part of the cap layer are removed to form a bonding pad window by a defined masking layer.

Abstract: The object of this invention is to provide a method whereby, during flip-chip connection using a thermosetting resin, it is possible to prevent the development of voids in the resin when the resin is hardened by pulse heating. The object is fulfilled by providing a method comprising heating a chip 4 to thereby harden a thermosetting resin 3 while applying a pressure to the chip 4 towards a substrate 1 to put a bump electrode 6 into contact with a wiring 2, wherein heating temperatures are adjusted appropriately according to:a first stage I of heating the thermosetting resin 3 to thereby spread it over the whole surface of substrate 1 which will carry the bump electrode 6 to thereby wet the surface with the resin 3;a second stage II of stimulating the gelation of thermosetting resin 3 by heating at a higher temperature than used in the first stage; anda third stage III of stimulating the hardening of thermosetting resin 3 by heating at a higher temperature than used in the second stage.

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.

Abstract: Reliable copper or copper alloy interconnection patterns are formed by forming a protective barrier layer lining a via or contact hole exposing an underlying conductive feature. Embodiments include forming a barrier layer on the insulating layer lining the side surfaces and on the exposed nitride layer before exposing a portion of the underlying conductive feature. The barrier layer prevents copper from depositing on the sidewalls of the dielectric interlayer and diffusing through the ILD.

Abstract: A method of making semiconductor devices comprising the steps of: preparing non-defective individual film packages having good quality, wherein leads are formed and a semiconductor chip is mounted on each of the film packages; attaching each of the non-defective individual packages to each of mounting portions of a plate; and cutting the plate into separate pieces, each of the separated pieces corresponding to each of the mounting portions on which each of the non-defective individual film packages is mounted.

Abstract: A method of manufacturing a semiconductor wafer in a chamber having a chuck and in which temperature changes in the chamber cause residual manufacturing materials to fall onto the surface of a production wafer placed on the chuck. When the temperature of the chamber is to be changed, a protection wafer is placed on the surface of the chuck. When the temperature has been changed, the protection wafer is removed from the surface of the chuck and a production wafer is placed on the surface of the chuck and clamped. When the process is complete the production wafer is removed and the protection wafer is placed on the chuck.

Abstract: A micro-electro-mechanical device and method of manufacture therefore with a suspended structure formed from mono-crystalline silicon, bonded to a substrate wafer with an organic adhesive layer serving as support and spacer and the rest of the organic adhesive layer serving as a sacrificial layer, which is removed by a dry etch means. Said substrate wafer may contain integrated circuits for sensing and controlling the device.

Abstract: In a method for manufacturing an integrated circuit arrangement, trenches that define active zones are formed in a substrate. A first insulating layer that fills the narrow trenches is conformally deposited and is structured with a mask and anisotropic etching such that spacers arise at sidewalls of the wide trenches and supporting locations arise in a region of the wide trenches. The surface of the active zones is uncovered by forming a second insulating layer with an essentially planar surface and by a planarizing layer erosion on the basis of chemical-mechanical polishing or conventional dry etching.