Abstract: A resin sealing film is formed on a silicon substrate by using a printing mask and a squeegee. The side surface in the tip portion of the squeegee is substantially V-shaped, and the printing is performed by pushing the tip portion of the squeegee into the gap between adjacent bump electrodes. As a result, the sealing film is formed in a manner to be depressed in the region between adjacent bump electrodes so as to facilitate the swinging movement of the bump electrodes. It follows that, in a temperature cycle test performed after the silicon substrate is mounted to a circuit substrate, the stress derived from the difference in thermal expansion coefficient between the silicon substrate and the circuit substrate is absorbed by the bump electrode.

Abstract: Disclosed is an optical semiconductor device which has: an optical semiconductor element; and a semiconductor element region provided as a peripheral circuit for the optical semiconductor element; wherein the optical semiconductor element is mounted on a semiconductor substrate that includes the semiconductor element region.

Abstract: A semiconductor device having lead terminals bent in a J-shape is disclosed. A radiating plate having a recess formed on an outer peripheral portion thereof is exposed to a lower face of a resin member and free ends of outer portions of the lead terminals are positioned in the recess of the radiating plate. The free ends of the outer portions of the lead terminals and the recess of the radiating plate are isolated from each other by projections of the resin member. Since the radiating plate is exposed to the lower face of the resin member, the heat radiating property is high whereas the radiating plate and the lead terminals are not short-circuited to each other at all.

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.

Abstract: A semiconductor package having an encapsulation that encapsulates an integrated circuit chip and an external lead frame for the chip. Multiple connection leads project from the periphery of the encapsulation. At least one external face of the encapsulation is covered with a layer of electrically conductive material, and the conducting material layer has at least one lateral extension that electrically contacts at least one of the projecting connection leads. A method of manufacturing such a semiconductor package is also provided.

Abstract: A method of manufacturing a leadless semiconductor chip package comprises the steps of: attaching a semiconductor die onto a die pad of a lead frame, wherein the lead frame comprises a plurality of leads arranged about the periphery of the die pad and each lead has a notch formed at the to-be-punched position thereof; wire bonding the inner ends of the leads to bonding pads on the semiconductor die; sucking a film against a lower part of a molding die; closing and clamping the molding die in a manner that the semiconductor die is positioned in a cavity of the molding die and the lead frame is disposed against the film; transferring a hardenable molding compound into the cavity; hardening the molding compound; opening the molding die to take out the molded product; and punching the molded product along the notches of the leads thereby making the singulation process more convenient and correct.

Abstract: In the manufacture of semiconductor packages having molded plastic bodies, the plating of all of the surfaces of the molding tool that comes into contact with the molten resin during molding with a nodular thin dense chromium (“NTDC”) coating prevents the surfaces from adhering to the package body and ensures good package release, without formation of cracks or craters in the package body. This, in turn, permits the amount of both release agents and adhesion promoters used in the molding compound to be substantially reduced, or eliminated altogether, thereby resulting in a package body having improved strength and adhesion with the components of the package, and hence, an improved resistance of the package body to the propagation of cracks and its subsequent penetration by moisture.

Abstract: A bond pad structure for use in wire bonding application during the packaging operation of semiconductor devices which contains a bond frame structure for holding the bond pad in place to prevent bond pad peel-off problem. The bond pad structure is a laminated structure containing a top dielectric layer, a metal bond pad layer, a middle dielectric layer, and an underlying layer formed above a wafer surface. The bond frame structure, which is formed in a spaced apart relationship from the metal bond pad layer contains a plurality of island elements formed on top of the middle dielectric layer and an interconnected frame element formed on top of the top dielectric layer. The frame element contains a portion which overlaps with a portion of the metal bond pad layer, so as to exert a downward force to prevent the metal bond pad layer from peeling off.

Abstract: A semiconductor structure with a backside protective layer and backside probes and a method for constructing the structure. Consistent with one embodiment of the invention, the semiconductor structure comprises a substrate having a first surface, on which a circuit interconnect layer is formed, and a second surface. A protective layer is formed on the second surface of the substrate, wherein the protective layer is non-reactive with gas used to etch the substrate. An electrically conductive probe extends from the protective layer through the substrate to an active region which is disposed in the substrate.

Abstract: A method of making a compliant interface includes providing a support structure and forming a plurality of compliant pads on the support structure by moving a sheet or mold having apertures toward a layer of flowable composition disposed on the support structure. A method of making a microelectronic package includes juxtaposing a microelectronic element with the compliant interface. Leads are formed between the microelectronic element and the substrate. An encapsulant may be disposed between the microelectronic element and the substrate.

Abstract: A semiconductor bare chip includes a plurality of stud bumps provided on the surface of the semiconductor bare chip body, each of the stud bumps including a seat and a head protruding from the seat. A height of the head is less than a thickness of electrodes on said board.

Abstract: A method for protecting the gate oxide layer of a MOS device. The method can also be used to monitor the intensity of radiation and charged particles falling on the gate oxide layer. The method includes the provision of a substrate having a gate structure thereon and an inter-layer dielectric layer over the gate structure, wherein the gate structure further includes a gate oxide layer and a gate electrode. Thereafter, a shielding layer is formed over the inter-layer dielectric layer, and then a protection diode is formed to link the shielding to the substrate.

Abstract: A method for forming through a dielectric layer a trench contiguous with a via. There is provided a substrate having a contact region formed therein. There is then formed upon the substrate a patterned first dielectric layer defining a via accessing the contact region, where the patterned first dielectric layer is formed of a first dielectric material which is not susceptible to etching with an oxygen containing plasma. There is then formed completely covering the patterned first dielectric layer and filling the via a the blanket second dielectric layer formed of a second dielectric material which is susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket second dielectric layer a blanket hard mask layer formed from a hard mask material which is not susceptible to etching within the oxygen containing plasma.

Abstract: A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.

Abstract: A method of forming an integrated circuit package at the wafer level. The integrated circuit package occupies a minimum amount of space on an end-use printed circuit board. Solder bumps, or conductive adhesive, is deposited on the metallized wirebond pads on the top surface of a silicon wafer. An underfill-flux material is deposited over the wafer and the solder bumps. A pre-fabricated interposer substrate, made of metal circuitry and a dielectric base, has a plurality of metallized through-holes which are aligned with the solder bumps. The wafer/interposer assembly is reflowed, or cured, to form the electrical connection between the circuitry on the interposer layer and the circuitry on the wafer. Solder balls are then placed on the metal pad openings on the interposer substrate and are reflowed to form a wafer-level BGA structure. The wafer-level BGA structure is then cut into individual BGA chip packages.

Abstract: There is provided a method of manufacturing a semiconductor device that ensures the connection state and enhance structural stability, reliability and heat-radiation performance. In a first step, metal bumps are joined to one of electrodes on a semiconductor chip and connection pads on a board. In a second step, the semiconductor chip is adhered to join means. In a third step, join means is joined with the board for connecting the metal bumps with the electrodes or the connection pads.

Abstract: A chip carrier and lid are sealed by mounting the chip carrier in an inverted position and mounting a lid having a sealing preform in an inverted position beneath and facing the chip carrier. The chip carrier and lid are then heated to melt the sealing preform and the chip carrier and lid are moved together to join them at the sealing preform.

Abstract: A process for forming a planar silicon-on-insulator (SOI) substrate comprising a patterned SOI region and a bulk region, wherein the substrate is free of transitional defects. The process comprises removing the transitional defects by creating a self-aligned trench adjacent the SOI region between the SOI region and the bulk region.

Abstract: An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.

Abstract: A metal is formed at a rear surface of a substrate, the substrate also having a front surface at which a molded semiconductor chip is mounted. The metal pattern is covered with an insulating film, except for at a connecting area. A solder ball is bonded to the connecting area. The area of the metal pattern other than the connecting area inclines toward the substrate and gradually becomes thinner toward the outside thereof. Stress, which is applied to the solder ball, is imparted in a diagonal direction and is dispersed. As a result, the number of occurrences of cracks is reduced, and the solder ball which is used to achieve connection with an external substrate, is effectively prevented form becoming electrically disconnected.