Abstract: The present invention relates to multilevel integrated circuit interconnection techniques. An integrated circuit having a number of electronic components along a semiconductor substrate and a first connection layer having a first number of conductors in selective electrical contact with the components is provided. A first insulative layer is formed on the first connection layer with a first pattern of openings therethrough. A second connection layer is established that has a second number of conductors selectively interconnected to the first conductors through the first pattern of openings. A second insulative layer is formed on the first connection layer with a second pattern of openings therethrough. A third connection layer is formed on the second insulative layer having a third dielectric and a third number of conductors selectively interconnecting the second conductors.

Abstract: Partial wafer processing is achieved by down loading the wafer map of the whole wafer from a host (12) and if the partial wafer contains the reference die (14) move table to a locator die (15) and upload locator die coordinates to wafer map data host (16) and remove other partial wafer die coordinates from the map (17). If the partial wafer does not have the reference die and is not the last partial wafer, position wafer table to auxiliary reference die (18), validate the auxiliary reference die position (19) and compute auxiliary reference die coordinates from locator die coordinates (20) and move wafer table to locator die (22) and upload locator die coordinates to wafer map data host (23) and then using auxiliary reference die and locator die coordinates as information remove other partial wafer die coordinates from the map (24).

Abstract: The second present invention provides a method of dividing a semiconductor wafer with an orientation flat into a plurality of pellets defined by both first scribe regions which extend in parallel to each other over the semiconductor wafer in a first direction parallel to the orientation flat and second scribe regions which extend in parallel to each other over the semiconductor wafer in a second direction perpendicular to the first direction. The method comprises the following steps. A metal film is selectively provided, which covers at least the first and second scribe regions. The metal film is selectively etched along longitudinal center lines of the first and second scribe regions by a lithography using a resist, so as to form metal masks, each of which comprises a pair of slender stripe masks separated from each other by a gap which extends on the longitudinal center line, so that longitudinal center parts of the first and second scribe regions are shown through the gaps of the metal masks.

Abstract: An optoelectronic device is mounted on a planar substrate in electrical connection with solder bumps adjacent an edge of the substrate and connection to a lead frame is made by loading the edge of the substrate on a lead frame support with lead frame conductors in engagement with the solder bumps and applying heat to melt the solder.

Abstract: Partial wafer processing is achieved by down loading the wafer map of the whole wafer from a host (2) and display the whole wafer in the die bonder monitor (3) move the wafer table to a first die pickup position (4) and move the display cursor to the first die pickup position (5) and teach two limit die coordinates in X direction (6) and teach two limit die coordinates in Y direction (7) and then using limit die coordinates as information remove other partial wafer die coordinates from the map (8) and select die pickup sequence (9).

Abstract: A process and system for connecting a semiconductor chip to a substrate is provided. The process includes providing the substrate that is configured to receive the semiconductor chip that has a bonding pad. The substrate has a first side that is suited to be connected to the semiconductor chip and a second side that is opposite the first side. The process then includes designing a metallization bonding structure on the first side of the substrate. The metallization bonding structure has a first end, a second end, and a bend defined between the first end and the second end. Then, an oxide passivation layer is defined over the first side that includes the metallization bonding structure. A bonding via is then defined through the passivation layer. The bonding via is configured to be aligned with the bend of the metallization bonding structure.

Abstract: The present invention provides an improved integrated circuit technique for increasing the reliability of wire-bonds in an integrated circuit by increasing the contact angle between certain pins and their respective wire-bonds, particularly those pins otherwise most susceptible to wire-bond failure, i.e., those pins conventionally located toward the corners of a conventional integrated circuit. By doing so, the overall length of the wire-bonds in a chip will be reduced, which in turn can result in further reduction of the probability of wire-bond failures. In a disclosed embodiment, a five or more sided integrated circuit shape is introduced wherein pads on up to four sides of an integrated circuit wafer chip are bonded to pins supported on eight edges of an integrated circuit package. An integrated circuit having at least five pin-supporting edges renders more robust wire-bond angles for any given integrated circuit package size.

Abstract: The present invention relates to the encapsulation for extending the lifetime of a flexible organic or polymer light emitting device and, more particularly, to encapsulation by sealing with multiple polymer films to prevent the penetration of oxygen and moisture into an organic or polymer light emitting device. Due to the encapsulation of polymer light emitting device with the multiple polymer films, exposure to moisture and oxygen are prevented, which are causes of device degradation. When using a plastic substrate whose the thermal endurance is high, simultaneously, it has a thermal endurance effect to the Joule heat during device operation. Accordingly, there can be fabricated an organic or polymer light emitting display whose lifetime is extended through the encapsulation of an organic of polymer light emitting device with multiple polymer films.

Abstract: A method for forming a metal line of a semiconductor device is suitable for forming a conductive material with strong connection force, by irradiating the region between metals to be connected with each other, with laser beams. It comprises the steps of: forming a plurality of metal lines on a substrate; depositing a first conductive material over the substrate including the metal lines; irradiating the first conductive material between the metal lines to be connected, with laser beams, before forming a second conductive material; and removing the first conductive material excluding the second conductive material.

Abstract: A method of exposing a bond pad includes: providing an integrated circuit having a bond pad, a first passivation layer overlying an area portion of the bond pad, and a second passivation layer overlying the first passivation layer; removing a portion of the second passivation layer above the area portion of the bond pad exposing an area of the first passivation layer; curing the second passivation; and etching a portion of the exposed area of the first passivation layer to expose the top surface of the bond pad. A method of coupling an integrated circuit chip to a chip package is also disclosed as is a method of probing the bond pads of an integrated circuit. A probe card is further disclosed, including a probe assembly coupled to a printed circuit board, the probe assembly having a sloped sidewall portion with a plurality of probing beams extending from the sidewall portion.

Abstract: A method of making a semiconductor device including: a ceramic base board formed of AlN; a CPU chip and a CMU chip which are flip-chip bonded on a circuit board which includes the ceramic base board; SRAM chips which are die-bonded to the lower major surface of the circuit board; first heat conductive blocks adhesively attached to the CPU chip and the CMU chip; second heat conductive blocks adhesively attached to the upper major surface of the AlN ceramic base board; a resin package; and a heat sink which, adhesively attached on the upper major surface of the resin package, is in close contact with the first heat conductive blocks and the second heat conductive blocks. The heat generated by the CPU chip and the CMU chip is transferred to the heat sink via the first heat conductive blocks and is radiated from the heat sink.

Abstract: A high performance semiconductor device structure and method of making the same include a bulk semiconductor substrate and an upper level silicon substrate. The upper level silicon substrate includes a low-K dielectric layer and a silicon substrate layer. The low-K dielectric layer is formed on the bulk semiconductor substrate, the low-K dielectric layer having a dielectric K-value in the range of 2.0-3.8. The silicon substrate layer and low-K dielectric layer are then patterned into the upper level substrate in a first region and the bulk semiconductor substrate is exposed in a second region. A gate oxide layer is formed over the upper level substrate in the first region and over the exposed bulk semiconductor substrate in the second region. Lastly, transistor device formations are formed in the upper level substrate and in the bulk semiconductor substrate.

Abstract: A method of forming a film on a substrate using Group IIIA metal complexes. The complexes and methods are particularly suitable for the preparation of semiconductor structures using chemical vapor deposition techniques and systems.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures are formed which compensate for misalignment between the via pattern and the trench pattern by widening the trench at the point where the misalignment has occurred. Methods and devices are also provided wherein the trench width is not affected by misalignment thus preventing electrical shorts between closely spaced interconnect lines, this technique results in a reduction of the width of the via. These dual damascene structures utilize two dielectric layers (210 and 216) having similar etching characteristics. Additionally, a hard mask layer (218) and an etch stop layer (214) having similar etching characteristics are used in these structures such that the etching characteristics of the dielectric layers are dissimilar to the etching characteristics of the hard mask and the etch stop layer. A trench (224) is formed in the hard mask layer (218).

Abstract: Multiplexed joining of solder bumps to various substrates for assembly of an integrated circuit package includes placing a semiconductor substrate (312) having solder bump structures (314) in contact with a ceramic substrate (320 having chip pads (322, 334), and placing this structure in contact with ball grid array spheres (352) in order to form a CBGA (360) in a single flow process.

Abstract: A method and apparatus are provided for forming cobalt on a silicon substrate containing native silicon oxide on the surface thereof wherein a modified vapor sputtering device is used. The vapor sputtering device is modified by providing an electrical circuit to ground whereby the wafer disposed in the device is electrically connected to the ground circuit. The ground circuit preferably contains a resistor therein to control wafer voltage and current flow from the wafer to ground. It has been found that providing a current flow from the wafer to ground and particularly in a ground circuit containing a resistor, provides an in-situ simultaneous cleaning of native oxide on the silicon surface and deposition of cobalt on cleaned silicon. The deposited cobalt containing substrate may then be readily annealed to form cobalt silicide evenly and uniformly across the desired regions of the wafer surface.

Abstract: A method is provided for controlling the critical dimensions of a polysilicon gate electrode, and for improving transistor drive current control. The method involves subjecting the gate structure of a transistor to a thermal treatment process in the presence of hydrogen gas. The thermal treatment process is performed subsequent to gate etching and photoresist mask removal, and provides gate electrodes having a more homogeneous linewidth, thereby improving transistor performance.

Abstract: A process for producing a semiconductor device having an interlayer insulating film of low dielectric constant and interconnects of low resistance and operable at a high speed, which comprises:a step of heat-treating a semiconductor substrate having a lower interconnect,a step of depositing, on the heat-treated semiconductor substrate, an insulating film having a dielectric constant of 3.5 or less,a step of making holes in the insulating film, anda step of growing a metal only in the holes by selective chemical vapor deposition.

Abstract: Semiconductor devices 340 are formed in semiconductor wafer 300. Contact pads 332 are formed in each die 330. An interconnect connects the contact pads 332 to die surface contact regions 210, 212. Scribe trenches 348 are formed in device wafer 300; corresponding trenches 358 are formed in cover wafer 360. The cover wafer 360 is thinned to open scribe trenches 348. Conductive vias 310-313 connect the contact pads 210, 212 to external surface bump contacts 333.

Abstract: A method for fabricating semiconductor components, such as packages, interconnects and test carriers, is provided. The method includes laser machining conductive vias for interconnecting contacts on the component, using a laser beam that is focused to produce a desired via geometry. The vias can include enlarged end portions to facilitate deposition of a conductive material during formation of the vias, and to provide an increased surface area for forming the contacts. For example, by focusing the laser beam at a midpoint of a substrate of the component, an hour glass via geometry is provided. Alternately, the laser beam can be focused at an exit point, or at an entry point of the substrate, to provide converging or diverging via geometries. The method can also include forming contact pins on the conductive vias by bonding and shaping metal wires using a wire bonding process, or a welding process.