Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

Abstract: A semiconductor device of a CSP structure is obtained by forming projection electrodes on a plurality of circuit element forming areas of a semiconductor wafer substrate, and then dividing the wafer into chips. Wiring patterns connected to connection pads for signal transmission are provided on the upper surface of an insulating film formed on the circuit element forming areas, and a conductive layer connected to a connection pad connected to a ground potential is provided on the resultant structure except for on the wiring patterns and on areas near the wiring patterns. Further, a thin film circuit element may be provided at the same layer as the conductive layer or below the conductive layer.

Abstract: A multi-hip semiconductor package is proposed, in which a first chip and a second chip are mounted on opposing surfaces of a lead frame in a staggered manner. This staggered arrangement assures the die bonding quality for firmly disposing the second chip in the semiconductor package without being detrimental affected by the first chip. Moreover, as both opposing surfaces of the lead frame have chips mounted thereon, a mold flow of a molding resin used in a molding process can be balanced, so that turbulence the mold flow is decreased, and void formation can be avoided. In addition, the semiconductor package can incorporate a third chip in a stacked manner with respect to the first or second chip. This therefore further improves the functionality and performance of the semiconductor package.

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.

Abstract: A plastic land-grid array package, a ball-grid array package, and a plastic leaded package for micromechanical components are fabricated by a molding process characterized by lining the cavity surfaces of the top and bottom mold halves with a protective plastic film, which also protects the surfaces of the components during the molding phase, selectively encapsulating the bonding pads and coupling members of the chip while leaving empty space above the components, and attaching a lid over the components. A molding method as well as a molding apparatus are provided compatible with the sensitivity of the micromechanical devices, yet flexible with regard to the technique used to assemble the chip and the substrate. Furthermore, the method disclosed is flexible with regard to the material and the properties of the substrate.

Abstract: A multi-chip, module (MCM) having one or more high value chips such as ASICs, CPUs, DSPs or the like attached to the MCM substrate via a direct attach technology (such as flip chip) and one or more memory chips attached to the MCM substrate via a reworkable technology such as connector and receptacle-based package, wirebond package, chip scale package (CSP), leaded package, ball grid array package, or fine pitch ball grid array package. The MCM substrate may, in turn, be attached to a motherboard via solder balls (ball grid array); leads and/or connector interconnect technologies (such as compression sockets).

Abstract: In a thin-film structure, since a flat face of a bump, which is exposed at the surface of an insulating layer and is to be in contact with an electrode layer, is an exposed surface of a nickel layer, an oxide layer on the flat face can be reliably removed by using ion-milling or sputter etching.

Abstract: A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), and a discharge layer (32) that is deposited to form a passivation (24) that protects the circuit (16) from electrostatic discharges caused by, e.g., a finger, is disclosed.

Abstract: A method for producing a chip module includes punching a chip carrier to form a chip carrier fixing section and chip carrier contact sections spaced apart from the chip carrier fixing section by slots defining a given distance. The given distance is subsequently reduced to a dimension preventing a flow through of a sealing mass by a swaging operation carried out at least in a region close to the slots.

Abstract: Semiconductor chips are formed on a wafer. The wafer is diced, while a dicing tape applied to the wafer is kept intact. Each of the semiconductor chips is fixed by suction and then removed from the dicing tape. Each of the semiconductor chips is unfixed by ceasing the suction and picked up and conveyed.

Abstract: A method of making a semiconductor chip package by attaching a chip to a dielectric layer; placing the dielectric layer and chip into a mold; disposing a thixotropic composition that has been sheared to reduce its viscosity into the mold and curing the thixotropic composition after the chip and dielectric layer have been removed from the mold. A method of making a semiconductor chip package without using a mold by disposing a sheared thixotropic composition between a semiconductor chip and a dielectric layer and then curing the thixotropic composition to form a cured encapsulant.

Abstract: A method for forming a back-to-back dual-chip package and package formed are disclosed. In the method, a first IC chip is bonded in its inactive surface to an inactive surface of a second IC chip, while solder balls planted on the active surfaces of both chips. One of the chips is connected to lead fingers of a lead frame by the solder balls. The dual-chip assembly together with the lead fingers are then encapsulated in an insulating material for protecting the chips while exposing substantially the solder balls on the IC chip that was not connected to the lead fingers. The encapsulated assembly can then be connected to an outside circuit, such as a printed circuit board, by forming the exposed finger leads for soldering and by fusing the solder balls to the outside circuit. The present invention novel method and device formed advantageously utilize existing chip design for achieving a high density device at a low cost.

Abstract: The present invention relates generally to a new apparatus and method for introducing thermal paste into semiconductor packages. More particularly, the invention encompasses an apparatus and a method that uses at least one preform of thermal paste for the cooling of at least one chip in a sealed semiconductor package. The thermal paste preform is subcooled, and is transferred onto a module component from a separable transfer sheet, or is placed onto the module component using an attached and/or imbedded mesh. The preform of thermal paste may be of simple or complex shape, and enables cooling of one or more chips in a module.

Abstract: A integrated circuit device and method for manufacturing an integrated circuit device includes forming a patterned gate stack, adjacent a storage device, to include a storage node diffusion region adjacent the storage device and a bitline contact diffusion region opposite the storage node diffusion region, implanting an impurity in the storage node diffusion region and the bitline contact diffusion region, forming an insulator layer over the patterned gate stack, removing a portion of the insulator layer from the bitline contact diffusion region to form sidewall spacers along a portion of the patterned gate stack adjacent the bitline contact diffusion region, implanting a halo implant into the bitline contact diffusion region, wherein the insulator layer is free from blocking the halo implant from the second diffusion region and annealing the integrated circuit device to drive the halo implant ahead of the impurity.

Abstract: A ball grid array (BGA) or chips scale package (CSP) integrated circuit (IC) (20) is manufactured by first identifying the most unreliable solder ball joints in the IC. These worst case joints, or joints in the vicinity of the worst case joints, are changed in pad dimension and exposed to more ball/bump conductive material than the other more robust joints (14) in the IC (20) to create a ball (24) on a larger pad (22) that is larger than the normal sized ball (14). The larger balls (24) are formed by placing multiple smaller balls (14) together on a single pad (22) to form one larger ball (24) during a reflow operation. The larger ball (24) improves the overall IC reliability by improving the reliability of the weakest joints in the IC design. In addition, the standoff of both the larger balls (24) and the smaller balls (14) are engineered to be substantially equal.

Abstract: The present invention discloses a dual-photoresist method for forming fine-pitched solder bumps on flip chips by utilizing two separate layers of photoresist, i.e., a first thin photoresist layer for patterning the BLM layers on top of the aluminum bonding pads and a second thick photoresist layer for patterning the via openings on top of the BLM layers to supply the necessary thickness required for the solder bumps. The first, thin photoresist layer permits an accurate imaging process to be conducted without focusing problems which are normally associated with thick photoresist layers. As an optional step, the present invention may further utilize a thin layer of non-leachable metal such as Cu or Ni for coating on top of the BLM layer and thus further improving the electrical characteristics of the solder bumps subsequently formed thereon.

Abstract: A method of producing a semiconductor device is described. The semiconductor device has a semiconductor chip with wiring terminals, conductor tracks for the electrical connection of the semiconductor chip, and a component of a housing configuration that contains organic, silicon-containing material. For this purpose, the semiconductor chip is applied to the component of the housing configuration and permanently connected to it. The conductor tracks and/or the wiring terminals are subsequently subjected to a cleaning process, in which silicon-containing material adhering to a surface is eliminated. The conductor tracks are subsequently connected in an electrically conducting manner to the wiring terminals. The contact quality of these electrical connections is noticeably improved by the cleaning process provided.

Abstract: A technique for fabricating precision aligned macros (PAMs) with reduced risk of electrostatic discharge damage and thermal damage. An electrical and thermal contact is provided through the back of the individual chips to a supporting silicon substrate. A conductive seed layer for electroplating is formed on a support substrate. A dielectric (preferably, a thermid) layer is formed on the seed layer. Vias are formed in the thermid layer and metal contacts are formed in the vias. The front faces of two or more chips are bonded onto the top surface of an alignment substrate, and the chips are aligned to the alignment substrate. The back faces of the chips are bonded to the metal contacts and thermid layer with heat and pressure. The alignment substrate is removed. The front faces of the chips are planarized. Finally, interconnect wiring is formed over the chips and thermid layer.

Abstract: A method of packaging a chip made in a semiconductor wafer. The method includes providing, on a first surface of the wafer, a conductive area extending beyond the periphery of the chip; adding a first thick plate including an electrically isolating material on the first surface; etching the conductive layer from a second surface of the wafer and depositing a conductive track extending from a contact of the second chip surface to the exposed surface of the conductive area; covering the second surface with a second thick plate forming a rigid cap; and etching the first plate above the conductive layer to deposit thereon a conductive material extending, in the form of a track, to the exposed surface of the first plate.

Abstract: A thermally enhanced package for an integrated circuit, the integrated circuit having a surface with bond pads formed thereon, includes a heat sink structure attached to a central region of the integrated circuit surface inward of the bond pads. The package further includes a substrate attached to the heat sink structure. The heat sink structure includes a heat sink and first, second adhesive layers between the heat sink and the integrated circuit, substrate, respectively. The heat sink enhances heat transfer between the integrated circuit and the substrate. Further, the first, second adhesive layers decouple any difference in thermal expansion between the integrated circuit, the heat sink and the substrate.