Patents Examined by Ngan Van Ngo
  • Patent number: 6809335
    Abstract: A plurality of gate lines extending in a horizontal direction are formed on an insulating substrate, and a data line is formed perpendicular to the gate line thereby defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line is formed in the horizontal direction, and a storage electrode connected to the storage electrode line and forming a storage capacitance by overlapping the pixel electrode is formed in the pixel. A redundant repair line both ends of which overlap the storage wire of the neighboring pixel, and a storage wire connection line connecting the storage wires of a neighboring pixel are formed.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: October 26, 2004
    Assignee: Samsung Electronics Co., LTD
    Inventor: Woon-Yong Park
  • Patent number: 6242794
    Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: June 5, 2001
    Assignee: Research Triangle Institute
    Inventor: Paul Enquist
  • Patent number: 5939742
    Abstract: A field-effect photo-transistor, being a three-terminal photosensing electrical device, based on integrated metal oxide semiconductor (MOS) technology. The device features a high output impedance which makes it particularly suitable as a photosensor for active pixel imaging arrays. Unlike the bipolar photo-transistor, which is a device well known in the art, the field-effect phototransistor is more compatible with MOS VLSI (Very Large Scale Integration) technology by inherently being a unipolar type device. Active pixel imaging arrays based on the disclosed invention can be integrated on the same semiconductor substrate with conventional digital or mixed signal processing functions to produce single-chip image processors for video or still picture cameras.
    Type: Grant
    Filed: February 10, 1997
    Date of Patent: August 17, 1999
    Assignee: Lucent Technologies Inc.
    Inventor: Aristides A. Yiannoulos
  • Patent number: 5907182
    Abstract: A semiconductor device which contains an electrode or an interconnection subjected to a high voltage prevents current leakage due to polarization of a mold resin. In this semiconductor device, a glass coat film 13a covering a semiconductor element has an electrical conductivity in a range defined by the following formula (1) under the conditions of temperature between 17.degree. C. and 145.degree. C.:conductivity.gtoreq.1.times.10.sup.-10 /E (1)(E: an electric field intensity ?V/cm!, E.gtoreq.2.times.10.sup.4 ?V/cm!)Owing to employment of the electrically conductive glass coat film, an electron current flowing through the conductive glass coat film suppresses an electric field caused by polarization of a mold resin.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: May 25, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tomohide Terashima
  • Patent number: 5844299
    Abstract: An integrated inductor with filled etch includes a substrate of semiconductor material which includes a surface and a cavity disposed therein, a mass of dielectric material disposed within the cavity, a layer of dielectric material disposed upon the mass of dielectric material, and a patterned layer of conductive material disposed upon the layer of dielectric material, such that the integrated inductor is formed without an oxide bridge. Thus, the integrated inductor has a rugged architecture.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: December 1, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Richard Billings Merrill, Donald M. Archer
  • Patent number: 5401995
    Abstract: An operational amplifier, of a type which comprises a differential cell transconductor input stage (2) incorporating a current mirror (5) provided with a pair of degenerative resistors (R9,R10) and a gain stage (7), driven directly by a transistor (Q12) of said mirror (5), has each degenerative resistor (R9,R10) formed within an epitaxial well wherewith a parasitic diode (D1,D2) is associated. Each diode (D1,D2) is connected in parallel with its corresponding resistor (R9,R10) to prevent the transistor (Q12) which drives the gain stage (7) from becoming saturated.
    Type: Grant
    Filed: July 30, 1993
    Date of Patent: March 28, 1995
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Ferdinando Lari, Pietro Erratico
  • Patent number: 5371392
    Abstract: A semiconductor apparatus connected between a signal input line and a grounding line is formed on a semiconductor substrate with a protection circuit connected between the signal input line and the grounding line, in parallel with the semiconductor apparatus. The protection circuit is formed, for example, of bipolar transistors, diodes, or MOS transistors.
    Type: Grant
    Filed: June 23, 1993
    Date of Patent: December 6, 1994
    Assignee: Sony Corporation
    Inventors: Hideto Isono, Hiroshi Hibi
  • Patent number: 5371384
    Abstract: Light emitting devices are formed on a surface of a solid state imaging device and are used as illumination light sources. In a solid state imaging device for use in an electro-endoscope or the like, an illumination light source need not be provided independently of the solid state imaging device. Hence, the electro-endoscope can be miniaturized and simplified in structure.
    Type: Grant
    Filed: June 24, 1993
    Date of Patent: December 6, 1994
    Assignee: Sony Corporation
    Inventor: Kazushi Wada
  • Patent number: 5369293
    Abstract: A charge-coupled device has a series register (A) having charge storage electrodes (3a) for defining charge storage wells and charge transfer electrodes (3b) for transporting charge between the charge storage wells and a parallel section (C) having channels (1a,1b) extending transversely of the series register (A). The parallel section (C) has charge storage electrodes (11a,12a,13a . . . Na) spaced apart along the channels, (1a,1b) to define a respective charge storage well with each channel to provide a respective row of charge storage wells extending transversely of the channels and has charge transfer electrodes (12b . . . Nb) for transferring charge between adjacent rows of charge storage wells, and a transfer gate (T1) for transferring charge between the series register (A) and an adjacent row of charge storage wells defined by the channels (1a,1b) and a first charge storage electrode (11a) of the parallel section.
    Type: Grant
    Filed: November 29, 1990
    Date of Patent: November 29, 1994
    Assignee: U.S. Philips Corporation
    Inventor: Arie Slob
  • Patent number: 5365081
    Abstract: A semiconductor device and a method for forming the same. The semiconductor device comprises an insulating or semiconductor substrate, a thermally-contractive insulating film which is formed on said substrate and provided with grooves, and a semiconductor film which is formed on the thermally-contractive insulating film and divided in an islandish form through the grooves. The thermally-contractive insulating film is contracted in a heat process after the semiconductor film is formed.
    Type: Grant
    Filed: March 27, 1992
    Date of Patent: November 15, 1994
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 5365093
    Abstract: A solid-state imaging device. An intermediate portion of a channel region have a tapered width from one shift register in which the signal charges to be read-out toward the other shift register. Therefore, the potential distribution of the channel region along the charge transfer direction has a continuous down-slope toward the one shift register. Thus, reading-out electric field can be improved.
    Type: Grant
    Filed: March 19, 1993
    Date of Patent: November 15, 1994
    Assignee: Sony Corporation
    Inventor: Yoshinori Kuno
  • Patent number: 5365098
    Abstract: A floating gate is formed via a first gate insulating film over the channel region between source and drain regions which are formed in a semiconductor substrate. A control gate is formed via a second gate insulating film over the floating gate. A low impurity concentration semiconductor region is formed on the side of the control gate which faces the floating gate. When erasing, a depletion layer is produced in this low impurity concentration region and further saturates the erase characteristic for the erasure time by decreasing the capacitance between the control gate and the floating gate.
    Type: Grant
    Filed: October 20, 1992
    Date of Patent: November 15, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Miyamoto, Kuniyoshi Yoshikawa, Kiyomi Naruke
  • Patent number: 5365092
    Abstract: A CCD which is designed and processed so that most of each pixel is covered only with an ultra-thin gate electrode so that the CCD can be frontside illuminated and still achieve good sensitivity in the ultra-violet and soft x-ray spectral range. More specifically, in the present invention, the usual three gate structure and corresponding polysilicon layers 1, 2 and 3 of conventional thickness are reduced in width and supplemented by a fourth ultra-thin layer of polysilicon dubbed herein, poly 4, that is deposited over the entire array. This fourth layer, poly 4, makes contact with poly 3, so that when poly 3 is driven, it also drives poly 4, thus allowing charge to collect and transfer as in a normal three phase CCD. However, because the deposition thickness of the poly 4 layer is on the order of 400 Angsttoms, as opposed to conventional thicknesses of 2000 to 5000 Angsttoms, poly 4 is essentially transparent to photons and thereby allows achievement of high quantum efficiency.
    Type: Grant
    Filed: February 8, 1993
    Date of Patent: November 15, 1994
    Assignee: California Institute of Technology
    Inventor: James R. Janesick
  • Patent number: 5359211
    Abstract: A high voltage protection circuit includes a breakdown network for providing a discharge path between a pair of terminal of a circuit to be protected. Each network conducts current between a supply terminal and another terminal at a low threshold voltage value when power is removed from the supply terminal. The network increases the threshold value when power is applied to the supply terminal to prevent conduction through the breakdown network during normal operation of the circuit to be protected. In one implementation, the protection circuit includes anti-latching circuitry connected to the breakdown network for preventing the breakdown network from latching on after or during the time power is applied to the supply terminals. To minimize the degradation of DC operating characteristics, the leakage currents, due to the protection circuit, between the first terminal and the positive supply terminal, and between the first terminal and the negative supply terminal cancel each other.
    Type: Grant
    Filed: July 18, 1991
    Date of Patent: October 25, 1994
    Assignee: Harris Corporation
    Inventor: Gregg D. Croft
  • Patent number: 5357136
    Abstract: A semiconductor device having a bonding pad region, and a method of its fabrication. A conductive layer is formed on an isolation layer separating transistors of the device, to anchor the interconnection layer on the bonding region. The conductive layer may be formed from the same layer of material that gate electrodes of the transistors are formed. An oxide insulation layer covers the conductive layer and has at least one opening exposing the conductive layer in the bonding pad region. A barrier metal layer, formed on the diffusion regions and the insulation layer, extends into the opening where it makes a firm direct connection with the exposed conductive layer. A bonding pad is formed on the barrier metal layer by providing the interconnection layer on the barrier metal layer. Since the conductive layer and the barrier metal layer are firmly connected, and secures the interconnection layer in the bonding pad structure.
    Type: Grant
    Filed: April 2, 1993
    Date of Patent: October 18, 1994
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kentaro Yoshioka
  • Patent number: 5349227
    Abstract: A semiconductor input protective device has an NPN type blpolar transistor and an N-channel MOS transistor. In the NPN type bipolar transistor, the collector is connected to a signal line and the emitter and the base are commonly connected to a ground line. In the N-channel MOS transistor, either the drain or the source is connected to the signal line and the other of either the drain or the source is connected to the signal line and the gate is connected to either the signal line or the power source line. The N-channel MOS transistor has a threshold voltage higher than the power source voltage. The NPN type bipolar transistor and the N-channel MOS transistor having a thick gate insulation film are used as input protection elements so that, even when a high voltage interface is effected, the function of the protective MOS transistor is not interfered with.
    Type: Grant
    Filed: October 15, 1992
    Date of Patent: September 20, 1994
    Assignee: NEC Corporation
    Inventor: Motoaki Murayama
  • Patent number: 5349216
    Abstract: A CCD image sensor comprising: a semiconductor substrate of a first conductivity type connected to a ground; an impurity region of a second conductivity type formed in the surface of the semiconductor substrate of the first conductivity type, to serve as a blooming prevention layer; an impurity region of the first conductivity type formed in the surface of the semiconductor substrate, so that it encloses the impurity region of the second conductivity type serving as a blooming prevention layer, to serve as a potential barrier layer; an impurity region of the second conductivity type formed in the surface of the semiconductor substrate of the first conductivity type so that it encloses the impurity region of the first conductivity type serving as a potential barrier layer, to serve as a light receiving region; an insulation film which is formed on the surface of the semiconductor substrate of the first conductivity type and has contact holes at both edges of the impurity region of the second conductivity type,
    Type: Grant
    Filed: June 11, 1993
    Date of Patent: September 20, 1994
    Assignee: Gold Star Electron Co., Ltd.
    Inventors: Seo K. Lee, Uja Shinji
  • Patent number: 5349212
    Abstract: A channel in which electron current is supplied from n.sup.+ type source layer to an n.sup.- type base layer is formed in a thyristor portion by using a first gate electrode to have an electrical connection in a thyristor state. Injection of hole current to a p type base layer, which is necessary to maintain the thyristor state is extracted to a source terminal by a control MOSFET portion including a second gate electrode a turn-off time and the state of this device is changed to the transistor state similar to that in the IGBT so that a short switching time turn-off is realized.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: September 20, 1994
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Yasukazu Seki
  • Patent number: 5347146
    Abstract: A thin film transistor comprising a multi-layer structure including an amorphous silicon layer and a metal layer both forming source and drain regions. The source and drain regions have opposite exposed edges with a slant shape. An active semiconductor layer is disposed at a channel region defined between the source region and the drain region so that it is overlapped with the upper surface portions of the source and drain regions adjacent to their edges faced to each other. In a CMOS type thin film transistor, its n type TFT has a gate overlapped with the source and drain regions and its p type TFT has a gate offsetted from the source and drain region.
    Type: Grant
    Filed: December 30, 1992
    Date of Patent: September 13, 1994
    Assignee: Goldstar Co., Ltd.
    Inventor: Hoe S. Soh
  • Patent number: 5345099
    Abstract: In a CCD device, on a semiconductor substrate, and in the insulation films, plural first semiconductor regions and plural second semiconductor regions are formed buried in the insulation films, intermediating a tunneling insulation film therebetween in a manner to spatially isolate them from each other.
    Type: Grant
    Filed: May 4, 1993
    Date of Patent: September 6, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Takahiro Yamada