Abstract: Long wavelength infrared detection is achieved by a detector made with layers of quantum well material bounded on each side by barrier material to form paired quantum wells, each quantum well having a single energy level. The width and depth of the paired quantum wells, and the spacing therebetween, are selected to split the single energy level with an upper energy level near the top of the energy wells. The spacing is selected for splitting the single energy level into two energy levels with a difference between levels sufficiently small for detection of infrared radiation of a desired wavelength.

Abstract: Described is a new high performance CCD image sensor technology which can be used to build a versatile image sensor family with the sensors that have high resolution and high pixel density. The described sensor architectures are based on a new charge super sweep concept which was developed to overcome such common problems as blooming and the image smear. The charge super sweep takes place in very narrow vertical channels located between the photosites similar to the Interline Transfer CCD devices. The difference here is that the charge is never stored in these regions for any significant length of time and is swept out using a new resistive gate traveling wave sweeping technique. The charge super sweep approach also allows the fast charge transfer of several lines of data from the photosites located anywhere in the array into the buffer storage during a single horizontal blanking interval.

Abstract: With the CCD imager of the present invention, signal charges from the image area are transferred by plural juxtaposed read-out registers. The storage region of the read-out registers, through which electrical charges are transmitted, is narrower in width at the image area side and broader in width at the other read-out register side. By virtue of such arrangement of the storage area, there is formed a potential which becomes shallow at the side of the image area and becomes deep at the side of the other read-out registers. By such potential, signal charge transfer efficiency between the read-out registers is improved.

Abstract: A semiconductor memory device is provided which includes a semiconductor substrate of a first conductivity type, a plurality of trench capacitors formed in the substrate and a plurality of switching transistors formed on the respective trench capacitors. Each of the switching transistors is electrically connected to the corresponding trench capacitor. Each of the trench capacitors has a first electrode formed in the side portion of a trench provided in the substrate and a second electrode containing impurities of the first conductivity type and embedded in the trench. Each of the switching transistors has a source region formed from a first epitaxial layer of the first conductivity type grown on the trench so as to electrically contact the second electrode, a channel region formed from a second epitaxial layer of a second conductivity type grown on the first epitaxial layer, and a drain region formed from a third epitaxial layer of the first conductivity type grown on the second epitaxial layer.

Abstract: An MOS semiconductor device has n.sup.30 -type source and drain regions in the main surface of a p.sup.30 -type monocrystalline silicon substrate. A p.sup.30 -type channel region is formed between the source and drain regions. A gate oxide film is provided on the main surface of the channel region, and a gate electrode is formed on the gate oxide film. In the portion of the monocrystalline silicon substrate between the source and drain regions, an inversion layer control region having an impurity concentration lower than that of the substrate is buried adjacent to the drain region. When a voltage is applied between the source and drain regions, the inversion layer control region maintains up to a high voltage an n-type inversion layer formed in the channel region.

Abstract: There is provided a pseudo bi-phase CCD having improved transmission efficiency that is easy for high-integration and can be designed by a simple process. The pseudo bi-phase CCD of the present invention has a gate electrode width which is reduced in a direction opposite to charge transmission direction in a gate electrode. In a charge coupled device having a plurality of gate electrodes formed on a semiconductor through which charges are transferred, the gate electrodes being separated by an insulation film, each of the gate electrodes includes a first part having a first width and a second width which is wider than the first width, the first width gradually increasing as it moves towards the second width formed in a direction of the charge transfer and a second part coupled to the first part, disposed in the charge transfer direction, the second part having the same width as the second width.

Abstract: A charge-coupled device having a three-dimensional trench structure that achieves a highly effective sensing and storage area in a CCD imager while maintaining a small cell layout area. The trench CCD device includes a plurality of trench electrodes etched in the surface of the device, with surface electrodes in between. The trenches are shaped to facilitate charge transfer along their sidewalls and to maximize trench surface area.

Abstract: A semiconductor device includes an InP substrate, an intrinsic InGaAs channel layer formed on the InP substrate and lattice matched to the InP substrate, a doped GaAsSb carrier supply layer formed on the intrinsic InGaAs channel layer and lattice matched to the InP substrate, a gate electrode formed on the doped GaAsSb carrier supply layer, and a source electrode and a drain electrode which are respectively formed on the doped GaAsSb carrier supply layer and located on both sides of the gate electrode.

Abstract: A small-area single-transistor EEPROM memory cell includes buried bit lines (44,46) extending through the array and connecting together many memory cells. Formed above a channel area (25) and between the bit lines (44,46) are oxide-nitride-oxide layers (50,52,54) for providing isolation between overlying polysilicon word lines (56, 66) and the underlying conduction channel (25). The nitride layer (52) provides the charge retention mechanism for programming the memory cell. The word lines (56, 66) provide electrical contact to a number of memory cells in the row. Electrical contact is made to the word lines (56, 66) by metal contacts (68, 70), and to the bit lines (44,46) by metal contacts (72, 74) at the array periphery, thereby avoiding metal contacts to every memory cell of the array. A EEPROM memory cell of 4-5.2 microns can be fabricated.

Abstract: In CCD arrangements, such as bidimensional image sensors, it is usual to provide the output register in the form of two (or more) horizontal registers. Via transverse connections between the horizontal registers, charge packets are transported from one horizontal register to the other horizontal register. In order to avoid delays during this transverse transport due to narrow channel effects, the clock electrodes of the first horizontal register adjoining the transverse connections are widened at the expense of adjacent clock electrodes. These widened electrodes may be in the trapezoidal form, as a result of which additional drift fields are induced below these electrodes.

Abstract: A semiconductor integrated circuit device comprising a negative differential resistance element, such as an RHET and RBT, and a field effect transistor, such as an SBFET and heterojunction type FET, which are formed on the same semiconductor substrate, a base layer of the negative differential resistance element and a channel layer of the field effect transistor being formed on the same epitaxial layer, and the same conductive material is used to simultaneously form an emitter electrode and a gate. A monolithic integration of both the element and transistor can be achieved both rationally and easily.

Abstract: An Acoustic Charge Transport Imager, suitable for use as a High Definition Television (HDTV) camera element, is disclosed in which an array of amorphous hydrogenated silicon based avalanche photodiodes are combined with acoustic charge transport channels in a GaAs substrate, to achieve very high speed read out of photogenerated charge. High speed read out allows the fabrication of detector arrays large enough to meet the resolution requirements of HDTV while ensuring operation within the timing constraints of the HDTV frame rate.

Abstract: An infrared or x-ray imaging CCD array, including deep trench isolation (56) for capturing electron carriers formed deep in the substrate (46) as a result of long wavelength radiation or high energy particles. In virtual phase CCD circuits, the trench has formed on the sidewalls thereof a diffusion (58, 60) defining a vertical conductor for allowing hole carrier conduction between the substrate (46) and the virtual phase electrode (38).

Abstract: Disclosed are a thin film transistor comprising a first electrode pattern formed on an insulating substrate as a gate electrode, a first insulating film formed as a gate insulating film and covering at least the electrode pattern, a semiconductor thin film pattern mainly composed of silicon formed on the insulating film, the semiconductor thin film pattern overlapping the first electrode pattern and the existing region thereof being limited, second and third electrodes formed on the semiconductor thin film pattern as a drain electrode and a source electrode, the second and third electrodes covering a portion of the semiconductor thin film pattern and being spaced apart each other, and a thin film containing silicon oxide formed over the semiconductor film, the second and third electrodes being formed upon the silicon oxide film, a method of manufacturing the thin film transistor, an active matrix circuit board using the thin film transistors, and an image display device using the active matrix circuit board.

Abstract: A resonant-tunneling heterojunction bipolar transistor (RHBT) device having a superlattice structure and a PN junction. The RHBT includes an emitter layer; a base layer; a collector layer operatively facing the base layer to form a PN junction at the face between the base layer and the collector layer; and a superlattice structure including at least one quantum well defining a sub-band of energy at which carriers resonant-tunnel therethrough, formed at least in the emitter layer and operatively facing to the base layer. The RHBT has a differential negative resistance characteristics for realizing a variety of logic circuits and includes an electron resonance and a positive hole resonance, for which the generation condition is changeable in response to a mole fraction of material of the emitter layer.

Abstract: A dual dielectric structure is employed in the fabrication of thin film field effect transistors in a matrix addressed liquid display to provide improved transistor device characteristics and also to provide both electricial and chemical isolation for material employed in the gate metallization layer. In particular, the use of a layer of silicon oxide over the gate metallization layer is not only consistent with providing the desired electrical and chemical isolation, but also with providing redundant gate metallization material to be employed beneath source or data lines for electrical circuit redundancy. Gate line redundancy is also possible. The electrical and chemical isolation provided by the dual dielectric layer reduces the possibilities of short circuits occurring in the display. The absence of short circuits together with the improved redundancy characteristics significantly increase manufacturing yield.

Abstract: A MOS FET comprises a pair of source and drain impurity regions, a gate oxide film and a gate electrode. The source and drain regions have an LDD structure in which high concentration impurity regions and low concentration impurity regions are set off. The gate electrode is formed to extend over the channel region and contains sidewalls overlying the low concentration impurity regions. In addition, portions of the gate oxide film located between the sidewalls of the gate electrode and the respective low concentration impurity regions are formed to have a film thickness larger than that of the portion located between the gate electrode and the channel region. The thick portion of the oxide film underlying the gate sidewalls form a charge storage layer which reduces the resistance of the low impurity concentration region while minimizing the gate capacitance. In another example, conductive sidewall spacers are formed on sidewalls of a gate electrode through an insulating film.

Abstract: A semiconductor layer, through which a main current flows, is so structured that a carrier life time in the semiconductor layer is ununiform in accordance with a predetermined distribution of the carrier life time. Thus, turn OFF characteristics of a semiconductor switching device can be improved without causing any unacceptable disadvantages for other characteristics.

Abstract: A floating gate junction filed-effect transistor image sensor element (10) is formed in a semiconductor layer (14). a drain region (20) of a first conductivity type of the elements (14) is formed adjacent a gate region (26). A potential barrier (98) is formed in the gate region (26) fo rcollecting carriers (102) of the second conductivity type, the barrier (98) also acting as a probing current well. A capacitor (28, 32, 48) is coupled to the gate region (26) and is operable to deliver a pulse to gate region (26) for sweeping out the carriers (102) to the substrate (12). The difference in gate bias voltage caused by the absence of the collected carriers (102) is sensed at a sense node (116) coupled to a source region (30).

Abstract: A photo-semiconductor device with a zero-cross function comprises a photo-trigger thyristor (11) which is controlled by an optical trigger signal, a MOSFET (13), and a Zener diode (14) formed in a monolithic manner in the same semiconductor substrate (16). A current path between the source and drain of the MOSFET (13) is connected between the gate and cathode of the photo-trigger thyristor (11) This MOSFET (13) is provided to control the gate sensitivity of the photo-trigger thyristor (11). The Zener diode (14) has its anode connected to the cathode of the photo-trigger thyristor (11) and its cathode connected to the gate of the MOSFET (13). This Zener diode (14) protects a gate insulating film (19) of the MOSFET (13) from dielectric breakdown. A light receiving portion (37) is provided in the Zener diode (14) and serves as a photodiode when the optical trigger signal is applied thereto.