Abstract: A semiconductor memory device having a non-volatile memory transistor and a selection transistor formed near the non-volatile memory transistor. The channel region surface of the memory transistor is formed to have the same conductivity type with a lower density than the channel region surface of the selection transistor or opposite conductivity type so that the characteristic of the memory transistor shifts to the negative side resulting in a sufficient read margin for an erased cell even at a control voltage of 0.

Abstract: In an MOS-controlled thyristor MCT comprising a multiplicity of adjacently disposed individual MCT cells (MC) having a cell width and which are electrically connected in parallel, either the MCT cells (MC) themselves or cell clusters (15) comprising a few closest-packed MCT cells (MC) are mutually separated by nonemitting gaps (2) which do not inject charge carriers into the cathode base layer and which have lateral linear dimensions greater than or at least equal to the cell width of the MCT cells (MC). As a result of this separation, the full performance of the individual MCT cell (MC) is achieved even in large-area components containing many cells.

Abstract: An image sensing device that outputs a signal logarithmically proportional to the intensity of the incident light. The image sensing device makes use of a sub-threshold current flowing between the drain and source of a MOS transistor when the gate voltage is below the threshold voltage (above which the MOS transistor is nominally conductive and below which nominally non-conductive). Since the logarithmic conversion is done in the photosensing section of a solid-state image sensing device, the output from the device is already compressed and is easily handled by a small capacity CCD. Some output systems for the image sensing device of the present invention are also described.

Abstract: The TFT structure formed in accordance with this invention includes a TFT body that has channel plug end sidewalls separated by a distance equal to or less than the width of the source/drain address lines and such that no residual doped semiconductor material adheres to the sidewalls. Similarly, the intrinsic semiconductor material layer is shaped such that no residual doped semiconductor material adheres to the sidewalls of the intrinsic semiconductor material layer underlying the channel plug ends.

Abstract: A horizontal charge transfer register has an array of charge transfer sections for transferring signal charges in a charge transfer direction, the charge transfer sections including a final charge transfer section. A floating diffusion region is connected to the final charge transfer section through a horizontal output gate section. A pair of potential barrier regions or a potential well region extends from the final charge transfer section to the horizontal output gate section, for orienting an electric field in the charge transfer direction in the horizontal output gate section. The potential barrier regions are spaced from each other by a distance which is progressively smaller from the final charge transfer section toward the horizontal output gate section. The potential barrier regions define a charge transfer path therebetween which is substantially the same as or close to the width of the floating diffusion region.

Abstract: A charge-coupled-device image sensor includes first, second and third linear array imagers, first, second and third horizontal charge-coupled-devices, first, second and third transfer gates and first and second vertically arranged charge-coupled-devices. The first transfer gate is operated so as to transfer electrons from the first linear array imager to the first horizontal charge-coupled-device. The third transfer gate, the first and second vertically arranged charge-coupled-devices and the second horizontal charge-coupled-device are operated so as to transfer electrons from the third linear array imager to the third horizontal charge-coupled-device. The second and third transfer gates and the first vertically arranged charge-coupled-device are operated after electrons from the third linear array imager have been transferred to the third horizontal charge-coupled-device so as to transfer electrons from the second linear array imager to the second horizontal charge-coupled-device.

Abstract: A solid-state charge-coupled-device imager has an imaging region composed of a matrix of vertically and horizontally arrayed photosensitive areas for storing signal charges depending on the intensity of applied light, and a plurality of vertical shift resisters for vertically transferring the signal charges shifted from the photosensitive areas. The signal charges from the vertical shift registers are shifted to a horizontal shift register that transfers the signal charges in a horizontal direction. The horizontal shift register comprises a plurality of charge transfer electrodes horizontally spaced at predetermined intervals. The charge transfer electrodes are inclined to the horizontal direction. The charge transfer electrodes may be inclined linearly in their entirety to the horizontal direction or may be of a chevron shape.

Abstract: The present invention is directed to an image sensor which comprises a body of a semiconductor material having therein a plurality of photodetectors arranged in a line and a CCD shift register extending along the line of photodetectors adjacent to but spaced from an edge of the photodetectors. The CCD shift register includes a channel region and a plurality of first and second gate electrodes extending over and insulated from the channel region. One of each of the first and second gate electrodes extends across a portion of the edge of each photodetector. Each of the first electrodes has an arm extending along the entire edge of its respective photodetector between the photodetector and the second gate electrode. A separate transfer region is in the body between the edge of each photodetector and its respective first electrode and extends along the entire edge of the photodetector. A transfer gate is over and insulated from the transfer regions.

Abstract: A wide dynamic range photodetector comprising a photosensitive region for generating signal electrons in response to being illuminated, a collection region for storing the signal electrons generated within the photosensitive region, a shift register for receiving and outputing the signal electrons from the collection region, and a transfer gate intermediate the photosensitive region and the collection region for alternately facilitating transfer of the signal electrons from the photosensitive region for storage in the collection region, and isolating the photosensitive region from the collection region while the signal electrons are being output via the shift register.

Abstract: A method of manufacturing a vertical bipolar transistor including the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of the first region, the extrinsic base region generally bounding a portion of the first region; forming by ion implantation a linking region of the second conductivity type in the surface of the bounded portion of the first region so as to electrically link generally opposing edges of the extrinsic base region through the linking region; forming an insulating spacer over the junction between the extrinsic base region and the linking region so as to generally bound a portion of the linking region within the portion of the first region; etching the surface of the bounded portion of the linking region a short distance into the linking region; forming by epitaxial growth a first layer of semiconductor material of the second conductivity type on the etched surface of t

Abstract: An interline transfer type area image sensor which operates in a non-interlaced mode and has an array of columns and rows of photoreceptor in which charge from each pixel is transferred into a stage of a vertical two-phase CCD shift register formed by adjacent electrodes of the CCD. Each electrode of a stage has a separate voltage clock. An ion implanted vertical transfer barrier region is formed under an edge of each electrode.

Abstract: A conductor attachment wherein each conductor is mounted on a dielectric tape and has an attachment portion that is supported by the tape to an adjacent location a uniform distance from the bonding location and that contacts on a level with the plane of the underside of the tape. One conductor supporting tape has portions of the tape that extend into a central contacting area opening to contact locations at contacting pads in rows remote from the edge. Another supporting tape has window openings at the contacting locations. The conductor ends are brought into the level of the underside of the tape by a manufacturing rolling operation between an elastomer surface roller and a solid backing roller.

Abstract: A novel concept and structure of a semiconductor circuit are disclosed which utilize the fact that the interaction between the carriers such as electrons and holes supplied in a meso-scopic region and the potential field formed in the meso-scopic region leads to such effects as quantum interference and resonance, with the result that the output intensity is changed.

Abstract: A semiconductor device is made by etching a III-V compound semiconductor layer having a (100) surface using a mask having an opening defined by edges including at least one edge along an [011] direction of the layer so that the surface revealed by etching has a (111) orientation. An electrode is formed on the (111) surface by vacuum vapor deposition.

Abstract: A field-effect, power-MOS transistor wherein a region under the gate contact pad is specially doped with a dopant that is electrically compatible with that in the transistor's channel to obviate problems of electrical breakdown in that region.

Abstract: An organic thin film and process for making the same, having electroconductivity, semiconductivity or superconductivity. The film is made of vapor-deposited bisethylenedithiatetrathiafulvalene (BEDT-TTF) by heating BEDT-TTF at a pressure of 10.sup.-2 Torr or below and at a temperature not higher than 260.degree. C. The temperature of the substrate on which the vapor is deposited is held at a lower temperature than the vapor. A thin film produced under these temperature and pressure conditions contains substantially no decomposition product. The electroconductivity of the film can be adjusted by selecting the substrate used for vapor-deposition of the film and the electron acceptor used as a dopant of the film. In order to achieve a vapor-deposited film with a high degree of orientation, silicon wafer is preferably used as a substrate for the film.

Abstract: The present invention is to provide a CCD delay line in which a deterioration of a charge transfer efficiency can be reduced by maintaining a charge amount treated in a charge transfer section provided at the rear stage of an intermediate output section. According to an aspect of the present invention, in a charge transfer device having charge transfer sections of a plurality of stages consisting of electrode pairs of a transfer gate electrode and a storage gate electrode and at least one intermediate output section provided at the rear stage of a charge transfer section of a predetermined stage from the signal input side, a cross-sectional area of at least one of the transfer gate electrode and the storage gate electrode in the charge transfer section provided at the rear stage of the intermediate output section is selected to be larger than that in the charge transfer section provided at the front stage of the intermediate output section.

Abstract: A solid-state imaging device of the invention is provided with a CCD-structured branching unit which selects one signal charge sensor having characteristics suitable for the conditions of use from among a plurality of signal charge sensors each having different characteristics and forms a signal charge transmission path leading from the horizontal CCD to the selected signal charge sensor. As a result, there is no need to switch over the external circuit of the solid-state imaging device according to the conditions of use, which makes it possible to hold down the cost and reduce the size of the external size.

Abstract: In a matrix array of photosensitive elements, each photosensitive point is provided with a photosensitive element (pin photodiode) in series with a capacitor between a row lead and a column lead. It is proposed to make use of a simplified photosensitive element in which an end semiconductor layer is suppressed such as, for example, the n-layer of a pin photodiode or the n-layer of a five-layer phototransistor of the nipin type. The dielectric of the capacitor then comes directly into contact with an intrinsic semiconductor layer in which electrons accumulate. These electrons reconstitute the equivalent of an n-type doped layer.

Abstract: A one-dimensional time-delay integration solid-state imager includes a plurality of light-to-electricity conversion parts which store signal charges generated in response to incident light, a vertical CCD corresponding to a series of the light-to-electricity conversion parts for transferring stored signal charges, and a gate for controlling transfer of signal charges stored at the light-to-electricity conversion parts to the vertical CCD. The signal charges corresponding to the same observed image moving on the plurality of light-to-electricity conversion parts are added to enhance the signal-to-noise ratio, and a background signal charge removing region for removing background signal charges is provided at the vertical CCD for removing background charges during the transfer of signal charges.