Abstract: A charge-coupled device includes a parallel section of parallel channels which are situated next to one another and are mutually separated by limitation zones, and a single readout register coupled thereto. The readout register is provided with clock electrodes in a multi-layer wiring system, the electrodes of the upper layer belonging to a common phase and being constructed as a continuous track which extends over the other electrodes. In the bottom wiring layer, electrodes are formed which are each associated with a limitation zone between the parallel channels and which have a length which is at most equal to the width of the limitation zones, and which also belong to a common phase, so that narrow-channel effects are avoided. The invention is of particular importance for CCD image sensors.

Abstract: A photosensitive device includes a semiconductor body (1) having a first region (2) of one conductivity type adjacent a given surface (3) of the body with a second region (4) of the opposite conductivity type surrounding the first region (2) so as to form with the first region a main pn junction (5) terminating at the given surface (3), the main pn junction (5) being reverse-biassed in operation of the device. One or more further regions (6) of the one conductivity type surround the main pn junction (5) adjacent the given surface (3) so that each further region (6) forms a photosensitive pn junction (17) with the second region (4), the further region(s) (6) lying within the spread of the depletion region of the main pn junction (5) when the main pn junction (5) is reverse-biassed in operation of the device so as to increase the breakdown voltage of the main pn junction (5).

Abstract: In a CCD device, a plurality of trench holes are formed in high resistivity semiconductor layer and juxtaposed in a charge transfer direction, and charge transfer electrodes are buried in the trench holes. Charge transfer regions are formed in the semiconductor layer around the vicinity of the respective trench holes during a main operating state.

Abstract: A charge coupled device (CCD) has a charge storage region and a potential barrier region. The CCD includes a first layer made of a first conductivity type semiconductor, a second layer made of a second conductivity type semiconductor and provided on the first layer, where the first and second conductivity types are mutually opposite types selected from n-type and p-type semiconductors, a third layer made of a first conductivity type semiconductor, impurity diffusion regions provided in at least a surface part of the third layer and having an impurity density higher than that of the third layer, a first gate electrode provided on the third layer between two mutually adjacent impurity diffusion regions, and a second gate electrode provided on each impurity diffusion region of the third layer. The impurity diffusion region forms the charge storage region of the CCD and the third layer between the two mutually adjacent impurity diffusion regions forms the potential barrier region of the CCD.

Abstract: A CCD shift register has a final transfer electrode which is formed only by a first polysilicon layer, and an output gate electrode which is formed by a second polysilicon layer. Under the output gate electrode, there is formed a doped region which is formed by a doping step of self alignment, independently of a doped region under the transfer electrodes. Therefore, it is possible to choose the impurity concentration and to adjust the potential level under the output gate electrode freely.

Abstract: An integrated circuit has a silicon mesa disposed on a substrate and a field insulator structure in proximity to the mesa and having an opening over a top mesa surface. The opening, which exposes sidewalls in the structure, is positioned with respect to the mesa and has dimensions such that the structure is disposed to overlap a region of the mesa along an outer mesa periphery. A layer of polysilicon extends along a top surface of the structure and into the opening and adjacent to the mesa top surface. An insulator is disposed between the poly layer and the mesa top surface, the insulator having a layer of thermal gate oxide disposed adjacent to the poly layer and having a layer of pyrogenic oxide disposed between the thermal gate oxide layer and the mesa top surface.

Abstract: A solid-state CCD imaging device has a substrate, photosensitive pixel cells provided as pixel sections in the substrate, and a transfer section, provided in the substrate, for transferring signal charge carriers read out from the pixel cells in a predetermined transfer direction. The transfer section has a semiconductive charge transfer channel layer formed in the substrate and transfer electrodes insulatively provided above the substrate and arrayed in the above direction while predetermined gap sections are kept therebetween. Each of the transfer electrodes defines one charge transfer stage. A gap potential control electrode layer is insulatively disposed above the electrodes.

Abstract: A dynamic latch circuit which is fabricated in a semiconductor integrated circuit comprises a first circuit such as a clocked inverter and a second circuit such as an inverter. The first and second circuits are connected by a holding line. In the semiconductor integrated circuit, at least three interconnection layers are provided on a semiconductor substrate to be insulated by insulating layers, such that the holding line is provided as the secondly highest interconnection layer, and an output line of the second circuit is provided as the uppermost interconnection layer to be positioned on the straight upper side of the holding line. For this structure, a coupling capacitance which is formed between the holding line and a through line connected to a third circuit and provided as the uppermost interconnection layer is decreased.

Abstract: A semiconductor apparatus for propagating light in a preferred direction which comprises, in succession, a substrate, a first emitter region, a first carrier confinement region, a first internal heterojunction barrier, a first base region, a second base region, a second internal heterojunction barrier, a second carrier confinement region, and a second emitter region, wherein portions of the first emitter region and the second base region are of one conductivity type and portions of the second emitter region and the first base region are of the opposite conductivity type, wherein the first and second emitter regions, the first and second internal heterojunction barriers and the first and second base regions together define a single optical cavity in the directions perpendicular to the preferred direction of light propagation, and electrodes are provided for applying an electrical current which flows through the semiconductor apparatus.

Abstract: In a charge transfer device, a low impurity density region is provided in its portion forming a floating capacitor. It becomes possible thereby to reduce the capacitance of the floating capacitor and thus to ensure a larger output voltage relative to a signal charge.

Abstract: A semiconductor device comprises a substrate of a first conduction type defined by a major surface, a pair of conductive regions of a second conduction type formed in the substrate along the major surface, an intervening region of the first conduction type formed in the substrate between the pair of conductive regions so as to separate the pair of conductive regions from each other, a first insulator film provided on the substrate so as to cover the major surface thereof including the pair of conductive regions and the intervening region located therebetween, a first conductor layer provided so as to extend generally parallel to the major surface of the substrate with a separation from the first insulator film, the first conductor layer crossing a part of the intervening region at a level separated therefrom, a second conductor layer provided on the first insulator film at a level below the first conductor layer so as to cover at least the part of the intervening region which is crossed by the first conductor

Abstract: A semiconductor device including a semiconducting layer made of polycrystalline silicon, an insulating film provided on an upper face of the semiconducting layer and an electrode provided on an upper face of the insulating film such that channels are formed on the upper face of the semiconducting layer, the improvement comprising: a further semiconducting layer made of amorphous silicon, which is provided between the semiconducting layer and the insulating film.

Abstract: A base resistance controlled thyristor with single-polarity and dual-polarity turn-on and turn-off control includes a turn-off device provided between the second base region and the cathode of a thyristor. Controlled turn-off is provided by either a near-zero positive bias or a negative bias being applied to the turn-off device. In the preferred embodiment, the turn-off device is a P-channel depletion-mode MOSFET in the surface of a semiconductor substrate. Accordingly, an accumulation-layer channel can be formed between the second base region and the cathode in response to a negative bias. Alternatively, if single-polarity control is desired, the P-type channel is provided to turn-off the device in response to a near-zero positive bias. In either type of operation, however, advantages are obtained over conventional turn-off devices wherein inversion-layer channels are used.

Abstract: A memory element is formed of a thin film transistor. The thin film transistor has a semiconductor layer, a source electrode electrically connected to the semiconductor layer, a drain electrode electrically connected to the semiconductor layer and formed separately from the source electrode, a gate electrode for controlling formation of a channel of the semiconductor layer, and a gate insulation film for isolating the gate electrode and the semiconductor layer from each other and causing a hysteresis in the relation between the drain current and the gate circuit. The insulation film is a silicon nitride film whose composition ratio of silicon to nitrogen is in a range of approx. 0.85 to 1.1. According to this invention, the relation between the gate voltage and the drain current can be set to have a hysteresis. Therefore, the thin film transistor can be used as a memory element.

Abstract: An integrated semiconductor circuit includes a substrate, an epitaxial layer having transistor base regions, a first and a second (11) insulating oxide layer, and a protective layer. The first oxide layer carries heavily doped polycrystalline layers, including an electric contact layer, a screening layer and a connecting layer. The connecting layer electrically connects the screening layer to the epitaxial layer, through the electric contact layer. The screening layer prevents the occurrence of inversion and parasite components in the epitaxial layer between the base regions. The polycrystalline layer arrangement is simple and can be produced in a common process step. The arrangement is able to withstand high temperatures and enables the second insulating layer to be readily applied.

Abstract: A structure of a solid-state image sensing device applicable to an HDVS is disclosed in which at least one of the transmission paths for the drive pulses used for driving vertical registers and horizontal registers can achieve reduced propagation delays and signal distortions of the drive pulses. In the first preferred embodiment, a control gate for controlling the transfer of signal charges between the horizontal registers is constituted by a first polycrystalline silicon layer, a metal wiring layer is formed and is connected to the first polycrystalline silicon layer via contact regions and transfer electrodes provided for driving the horizontal registers are constituted by second and third semiconductor layers placed between the first polycrystalline silicon layer and the metal wiring layer without contacting the contact regions.

Abstract: An heterojunction field effect transistor comprises a channel forming layer associated with a carrier supplying layer, and an electrostatic lens is provided across the channel forming layer with a focusing gate electrode appropriately biased, wherein an abrupt potential discontinuity is produced in the bottom edge of the conduction band of the channel forming layer with an emitter gate electrode provided between a source electrode and the focusing gate electrode so that hot electrons produced by the abrupt potential discontinuity have substantially uniform longitudinal electron energies allowing the hot electrons to be focused upon a focal point of the electrostatic lens.

Abstract: An output circuit for sequentially receiving and converting charge collected in the photoelements of an image sensor and converting such charge into an output voltage. The output circuit includes a buried-channel LDD transistor having gate, source and drain electrodes. The source electrode provides a floating diffusion. When the transistor is turned off, a potential well is provided in the floating diffusion which collects charge. An output source-follower amplifier also employing buried-channel LDD transistors is connected to the floating diffusion and produces the output voltage.

Abstract: A charge coupled device includes a second conductivity type first horizontal channel in a first conductivity type semiconductor substrate, a second conductivity type second horizontal channel in the substrate at a predetermined distance from the first horizontal channel, and a second conductivity type transfer channel connecting the first horizontal channel with the second horizontal channel to enable transfer of charges from the first horizontal channel to the second horizontal channel. The pinning potential of the transfer channel is larger in absolute value than the pinning potential of the first and second horizontal channels, and the gate voltage pinning the transfer channel is smaller in absolute value than the gate voltage pinning the first and second horizontal channels.

Abstract: A low capacitance radiation detector comprises a monocrystalline silicon substrate heavily doped to N type conductivity with a more lightly doped N type conductivity epitaxial layer formed on the substrate. A plurality of heavily doped N type upper surface layer segments are formed in the epitaxial layer. A patterned region of the epitaxial layer, heavily doped to P type conductivity and in the shape of parallel stripes joined at each end by a respective stripe perpendicular to the parallel stripes, is formed in the epitaxial layer and situated between adjacent ones of the upper surface layer segments, with each stripe extending into the epitaxial layer deeper than, and separated from, the upper surface layer segments so as to form a minority charge carrier-collecting PN junction with the epitaxial layer.