Abstract: A selectively definable semiconductor device is provided. In one form, a composite gate array includes a plurality of logic dedicated general purpose cell regions and a plurality of function dedicated cell regions each of which is disposed between the two corresponding ones of the plurality of logic dedicated general purpose cell regions, whereby each of the cell regions may be used as an interconnection region selectively. In another form, a semiconductor memory device which may be selectively defined as a ROM or a RAM by a metalization process is provided.

Abstract: A highly integrated semiconductor memory device having one transistor type memory cells is disclosed. The capacitor and transistor of the memory cell is provided within and around one trench formed in the semiconductor substrate. The channel region of the transistor is positioned along the side wall of the trench with a ring shape in the plan view and the capacitor element is surrounded by the transistor within the trench.

Abstract: A CMOS technology cell which can be formed as a resistor, a capacitor, a resistor capacitor combination or a load impedance in a gate array wherein a basic cell is replaced by a special cell which has the same geometrical dimensions as the special cell. The special cell contains a pair of transistors (Tr1 and Tr2) with channels KP, KN of the transistors which are narrow but have long lengths. The transistors are arranged laterally to the source and drain of the transistors and due to the long channel length of each transistors, the transistors can be used as a resistor having a substantial resistance value. Also, the gate capacitance can be used as a high value capacitor thus allowing the special cells to provide resistance, capacitance, RC or load impedance for the other cells.

Abstract: An improved LCMOS display device employing a silicon-on-insulator (SOI) substrate having an epitaxial silicon layer lying over an implant-generated dielectric layer. MOS device and capacitor elements used to activate the display are formed and interconnected in the epitaxial silicon. The implant-generated dielectric layer and underlying silicon substrate also serve as capacitor elements, thereby simplifying the structure and fabrication of the display device and providing improved operation through improved isolation of the MOS device elements formed in the epitaxial silicon from the substrate.

Abstract: A dual-gate vertical field effect transistor comprises an N+ substrate (102) which serves as a drain, and N-epitaxial layer (104) formed on the N+ substrate, and an N+ layer (106) formed at the surface of the epitaxial layer which serves as a source. A plurality of grooves (108a, 108b) extends through the N+ region and a portion of the N-layer. The grooves are lined with an insulating layer (110a, 110b) and filled with a conductive polysilicon gate (112a, 112b). Underneath each of the grooves is a P+ region (116a, 116b) which serves as a second gate. Thus, the transistor in accordance with the present invention includes a set of polysilicon gates and a set of P+ gates for independently modulating the current permitted to flow between the transistor source and drain.

Abstract: A switch is provided that introduces quasiparticles at an asymmetric location into a reduced cross-sectional area microbridge link that is part of an output path. The quasiparticles nucleate a small region of normal resistivity and the normal region propagates to produce normal resistivity in the entire reduced cross-sectional area microbridge link. The asymmetry of the location provides input-output isolation. The high critical current, high resistivity material for the reduced cross-section member provides high current and voltage gain and the small size provides high speed. In one structure, an input film conductor is asymmetrically, centrally positioned in an insulator stack and a microbridge like is positioned on a beveled side of the stack with the input conductor in tunneling relationship with part of the narrow portion of the microbridge link. Decoupling between input and output sufficient to permit one switch to drive several others is provided.

Abstract: The invention provides a variable capacity diode with a plane structure so that it may be formed in an integrated circuit, this diode has, on the substrate, three coplanar regions. The first and second uniformly doped regions support the contact making metallizations. The transition region has a variation of doping level, low at one end and high at the other end. This variation is obtained by implantation by means of a focused ion beam, with constant energy and sweeping at increasing doses, which allows a hyperabrupt profile to be obtained. The diode is a p-n junction of Schottky contact diode.

Abstract: An integrated circuit semiconductor device having an improved power supply wiring structure is disclosed. The wiring includes a wide conductive layer and a plurality of stripe type narrow conductive layers formed on the wide conductive layer via an insulating film. Each of stripe type conductive layers is connected to the wide conductive layer through a plurality of contact holes provided in the insulating film.

Abstract: A protection system for CMOS integrated circuits to prevent inadvertent damage caused by electrostatic discharge includes a low impedance power supply bus structure and a plurality of bipolar and MOS clamping networks. The bipolar clamping networks are formed around each of the bonding pads for interlinking all of them together through the low impendance power supply bus structure. When any one of the bonding pads receives a higher voltage than a predetermined value and another remaining one of the bonding pads contacts a ground potential, current is routed from the one bonding pad through the low impedance power supply bus structure to the other bonding pad in order to discharge the same.

Abstract: A photoconductor comprising an optically sensitive FET in which an abrupt heterojunction (18) is inserted in the channel (11) at a certain distance from the gate contact (16). This provides a potential barrier (17, FIG. 4) in the valence band that accumulates minority carriers (carriers of the lower mobility type) and controls their release. A gate bias resistor which is conventionally used in a receiver circuit including the FET is no longer required, instead the potential barrier height determines the time constant and a response comparable in length with an input optical pulse is achieved. This overcomes the problems of integrated manufacture, and slow response, associated with the large value of the bias resistor which is needed to reduce noise.

Abstract: A semiconductor light receiving device comprising: a light receiving section obtained by arranging a plurality of light receiving elements having pn junctions in an array on a semiconductor substrate; a signal taking out section for taking out an electric signal obtained at the light receiving section; and a member for applying a magnetic field having a component in a direction vertical with the surface of the semiconductor substrate to the light receiving section.

Abstract: The invention relates to an optoelectronic component for surface mounting of the type having an opto-electronic element arranged on the bottom of a cavity provided in a support and to the method of manufacturing same. The component includes a cavity coated with a metallization coating. The optoelectronic element is soldered on the bottom of the cavity. The support is a substrate of Si strongly doped with the first conductivity type, whose surfaces are orientated according to the plane (100), while the metallized surfaces of the cavity are formed by the preferential attack according to the planes (111). Regions of the second conductivity type are diffused into the cavity and into a cavity merging into the latter from the lower surface of the substrate. The element is soldered with suitable polarity, and insulation is provided by a diode connected with reverse polarity in parallel with its terminals. The contact points at the lower surface of the substrate permit surface mounting.

Abstract: Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions of the two driver MOS transistors in each memory cell are connected in common and further connected to a ground potential point through a second-level conductive layer. The two load resistances in each memory cell are formed from a third-level high-resistance material layer. The second-level conductive layer is formed from a low-resistance material layer. Thus the resistance of the sources of the two driver MOS transistors is lowered.

Abstract: The word line pitch within a read-only memory is decreased, thereby increasing the cell density within the memory, without imposing any additional or stricter spacing rules or fabrication techniques utilized in the manufacture of the read-only memory integrated circuit chip. The read-only memory is comprised of a plurality of memory cells. A two-dimensional semiconductor diode layer is laid down on a plurality of word lines which have previously been disposed upon a semiconductor supporting substrate. The semiconductor diode layer is disposed on the plurality of word lines without regard to any alignment criteria. A programmable material is inlaid on the Schottky diodes and a plurality of bit lines laid upon the programmable material. The bit lines and word lines are orthogonally disposed with respect to the Schottky diodes so that each diode is uniquely addressed by one word line and one bit line.

Abstract: An Ohmic contact to a semiconductor body includes a thin semiconductor layer disposed between the body and a conductive layer. The thin layer is not alloyed to the conductive layer and not lattice matched to the body. The layer can have a thickness of less than about 100 nm and a lattice mismatch of at least 0.5 percent. Since the thin layer is not alloyed, a Schottky contact can be formed at the same time as the ohmic contact.

Abstract: Heterojunction HgCdTe detector has in order, a first type P Hg.sub.1-x.sbsb.1 Cd.sub.x.sbsb.i Te monocrystalline semiconductor layer, x.sub.1 being a number between 0 and 1, containing a first type P region, a second type P Hg.sub.1-x.sbsb.2 Cd.sub.x.sbsb.2 Te monocrystalline semiconductor layer, x.sub.2 being a number higher than x.sub.1 between 0 and 1, containing a second type N region which faces and is in contact with the first region, an electrical insulant located above the first semiconductor layer and an electric contact element located on the insulant for collecting the electric signal produced in said first region, said contact element having a part traversing the second region and partly penetrating the first region with application to infrared radiation detection.

Abstract: An integrated circuit includes a substrate of one conductivity type silicon and an epitaxial layer of the opposite conductivity type silicon on a surface of the substrate. An emitter region of the one conductivity type is in the epitaxial layer and a collector region of the one conductivity type is in the epitaxial layer and extends around but is spaced from the emitter region. A third region of the one conductivity type is in the epitaxial layer and extends partly around and is spaced from the collector region. A highly conductive connector region of the opposite conductivity type extends into the epitaxial layer to a buried region of the opposite conductivity type which is along the junction of the epixtaxial layer and the substrate. The connector region contacts the third region. A thin layer of silicon oxide extends over the epitaxial layer. Separate contacts extend through the epixtaxial layer to the emitter region, collector region and to adjacent portions of the third region and the collector region.

Abstract: A semiconductor device includes a multilayer semiconductor structure comprising alternately p- (or n-) type heavily doped semiconductor layers and n- (or p-) type lightly doped semiconductor layers. Holes (or electrons) are confined within a narrow layer in a fashion like a two-dimensional gas, whereby high mobility is realized notwithstanding of high carrier concentration. Electrical conductivity of the multilayer semiconductor structure can be made higher than that of a bulk semiconductor. Very high conductivity can be realized by forming each layer in a thickness within a range of 10 .ANG. to 1000 .ANG. and preferably 50 .ANG. to 500 .ANG.. Ratio in impurity concentration of the heavily doped layer to the low doped layer is not smaller than one order of magnitude.

Abstract: Silicon doping of GaAs provides n conductivity in {100} planes and p conductivity in {111} A planes. A split level of Si-doped GaAs utilizes this phenomena to provide a bipolar transistor. In one embodiment, the emitter is one level of the layer in the {100} planes, and the collector is another level of the layer in the {100} planes. These n conductivity levels are joined by {111} A planes to form a p conductivity base. The junctions in the layer between the {100} planes and the {111} A planes form an npn transistor.

Abstract: The disclosure is directed to integrated circuit chips and particularly to "gate array", or "master slices" whereon one or more circuits drive a highly capacitive on chip wiring net. The driving circuits are modified and a compensation circuit coupled to the highly capacitive on chip wiring net to mitigate the burden caused by the high capacitance. The integrated circuit structure also contains efficiently positioned on each chip a number of compensation circuits which are readily connectable during the fabrication of the chip. The employment of one, or a number of, on chip compensation circuits does not materially increase the chip power consumption.