Abstract: An insulated gate SIT (IBCM-SIT) which is substantially free from punch-through and hot carriers and exhibits a triode characterisic. Also, an insulated gate SIT (ISIS-SIT) which exhibit a tetrode or pentode characteristic, not by an r.sub.s feedback effect, but by the addition of a static shield region. When those devices are used to construct a complementary circuit, no significant latch-up occurs.

Abstract: An improved integrated circuit structure is disclosed comprising MOS devices formed with at least raised polysilicon gate contact portions. Metal silicide is formed over at least a portion of the source and drain regions to provide conductive paths to the source and drain contacts. In a preferred embodiment, the source and drain contacts also comprise raised contacts which are also formed from the same polysilicon layer to permit formation of a highly planarized structure with self-aligned contacts formed by planarizing an insulating layer formed over the structure sufficiently to expose the upper surface of all of the contacts.

Abstract: Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n.sup.- and n.sup.+ regions in GSDs and LDDs.

Abstract: A semiconductor chip circuit device includes cell arrays having pairs of an n-channel device formation region and a p-channel device formation region. Conductive power source lines are selectively formed between the pairs and are situated in grooves in the substrate. The conductive lines are selectively connected to impurity introduction regions in each formation region of each pair. An insulating layer is formed in the grooves over the conductive lines, and wirings selectively connect a plurality of pairs formed on the insulating layer.

Abstract: In a dynamic memory for capacitive data storage, enhanced data storage and transfer performances are achieved on the one hand by increasing the value of storage capacitance and on the other hand by increasing the conductivity of the transfer lines. The word lines of the memory cells are metallized in order to increase the speed of propagation of reading and/or writing instructions. Metallization of the word lines makes it possible to cover the memory cell with a second polysilicon layer followed by a third polysilicon layer in order to increase the data-storage capacity.

Abstract: A semiconductor device wherein a coating film which is made of a polyimide resin or a polyimide isoindoloquinazolinedione resin and which is at least 10 .mu.m thick is disposed on at least an active region of a semiconductor substrate, and the resultant semiconductor substrate is encapsulated in a ceramic package. The semiconductor device has troubles relieved conspicuously, the troubles being ascribable to alpha-rays which come flying from impurities contained in the material of the package.

Abstract: A multilayer interconnect and method of forming the same between first and second overlying conductive strips separated by an insulating layer having an aperture therethrough. The improvement wherein at least one edge of the first strip is aligned with an overlying edge of the second strip. The interconnect is formed by depositing the second strip on the insulating layer such that it at least partially overlaps the aperture and extends beyond an edge of the first strip. The second strip and first strip are then partially removed such that at least one edge of the first and second conductive strips are aligned.

Abstract: A single layer of polycrystalline silicon (poly-Si) is used in an EEPROM structure, which obviates the need to form a separate control gate and floating gate. The EEPROM utilizes three separate NMOS transistors: a write transistor, a read transistor, and a sense transistor. A thin tunnel oxide layer separates the N+ source region of the write transistor from an N doped poly-Si layer and capacitively couples the source region to the poly-Si layer. The poly-Si layer extends over the N+ source region of the sense transistor and is capacitively coupled to the source region of the sense transistor via a thin gate oxide insulating layer which is thicker than the oxide layer comprising the tunnel oxide layer. This poly-Si layer continues to extend over a channel region separating the N+ source and N+ drain regions of the sense transistor, the poly-Si layer being separated from the channel via the thin gate oxide insulating layer. The drain of the sense transistor also acts as the source of the read transistor.

Abstract: An improved planarization and reliability for low-impendance interconnects in multi-layer wiring of integrated semi-conductor circuits is provided. The circuit comprises at least two metallization levels composed of aluminum or of an aluminum contact, tungsten is employed as a via hole filler and metal silicides are employed as intermediate layers. The metallization pattern contains a nucleation layer preferably composed of titanium/titanium nitride as an under-layer for every metallization level, whereby the electron migration resistance of the aluminum layers is enhanced and a layer preferably composed of molybdenum silicide is used as a cover layer for every metallization level, thereby improving the low-impedance of the metallization. The sandwich-like metallization structure improves the planarity and the thermal stability of the circuit. Since the number of metallization levels is arbitrary, the present invention can be used for VLSI circuits.

Abstract: A field programmable device such as a PROM in which a memory cell is formed from a series connection of a capacitor and a diode or FET. Programming is performed by forming a short circuit in an insulation film of the capacitor due to electrical breakdown of the capacitor. The capacitor is formed of first and second semiconductor layers and an insulation film between the two layers. The instability of short circuits due to further oxidation of the insulation film is avoided by the above described structure. The memory stored in the device is stabilized, and the reliability of the device is increased. The insulation film of the capacitor is oxidized or nitrided by ion implantation of oxygen or nitrogen into the semiconductor substrate, or polycrystalline material.

Abstract: An improved integrated circuit structure is disclosed comprising bipolar and MOS devices formed on the same substrate. The bipolar devices have at least the emitter and the collector contact portions formed from a polysilicon layer which results in raised contacts. The MOS devices are similarly formed with raised gate contact portions formed from the same polysilicon layer. Metal silicide is formed over at least a portion of the base, source, and drain regions to provide conductive paths to the base, source, and drain contacts. In one embodiment, the base, source, and drain contacts are also formed from the same polysilicon layer to permit formation of a highly planarized structure with self-aligned contacts formed by planarizing an insulating layer formed over the structure sufficiently to expose the upper surface of the contacts.

Abstract: A power MOS transistor includes a polycrystalline silicon layer which provides connection to act as a resistor between a first portion of gate metallization disposed above the gate of the device, and a second portion of gate metalization adjacent to the active source/gate region of the device.

Abstract: A photoconductive detector comprises a substrate layer of semiconductor material of a first conductivity type substantially transparent of light at the wavelength to be detected and doped sufficiently to provide ohmic contact to the photoconductive active region overlying said substrate layer. The active region comprises a body of undoped semiconductor material absorptive of light at the wavelength to be detected, having first and second major surfaces. The substrate layer serves as a first ohmic contact for the entire first major surface of the active region and a metal or metal alloy serves as a second ohmic contact overlying the entire second major surface of said active region.

Abstract: A junction field effect transistor formed on insulator substrates particularly oxide substrates and having a polysilicon vertical control gate region formed of a cross member and two end members orthogonal thereto. The vertical control gate is formed over an n-channel in a Si island, the n-channel is located beneath the cross member, with p.sup.+ junction gate regions laterally disposed on either side of the n-channel and n.sup.+ drain and gate regions laterally orthogonal thereto in Si island.

Abstract: Field isolation between arrayed picture cells of an image sensor is fabricated thinner than the insulation layer for the peripheral portion of CCD operatively connected to picture cells. The field isolation is fabricated by a selective thermal oxidization, by which the isolation film inflates not only vertically but also laterally, therefore the thinner isolation layer can be narrower. And, the lower applied voltage to the picture cell than applied voltage to the CCD portion allows the narrower isolation. The narrower field isolation between the picture cells allows greater density of integration of the picture cells. Procedures to embody the invention are disclosed, one of which is to fabricate the thinner isolation first, and another one is the thicker insulation layer first.

Abstract: A means and method for providing platinum or tungsten silicide contacts to source, drain, gate and tub regions of a dielectrically isolated MOSFET is described. A "false" gate is used to provide automatic self-aligned separation of the source-drain contact and the tub contact. An intermetallic forming material is uniformly coated over the doped substrate on which the gate and false gate region have been formed in a spaced-apart fashion. Upon heating the intermetallic forming layer reacts with the substrate and the polysilicon gates to form intermetallic regions. The remaining portion of the intermetallic forming layer is differentially etched away from the dielectric isolation walls and the sidewall oxides on either side of the gate and false gate. Alernatively, selective deposition may be used to avoid deposition on the dielectric regions. The false gate extends laterally across the isolation tub. This procedure separates the device contacts from the tub contact without the use of separate masking layers.

Abstract: An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment members and a heavily doped junction is aligned with the outboard alignment members.

Abstract: A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.

Abstract: A charge-coupled semiconductor device has a plurality of silicon electrodes for storing and transporting information-carrying charge, which electrodes are located on an insulating layer and are mutually separated by grooves having a width of at most 1 .mu.m. According to the invention, transfer electrodes are arranged in the grooves, these electrodes being coplanar with the remaining electrodes. The thickness of the insulating layer under the transfer electrodes is substantially equal to that under the storage electrodes. The invention also relates to a method of manufacturing a semiconductor device having such an electrode system.

Abstract: The invention relates to a charge-coupled device with an adjustable charge transport route having at least two ccd segments, which can be connected in series with each other by means of a switchable connection. This connection includes an output diode for the first segment, an input diode for the first segment, an input diode for the second segment and a switch, for example a MOS transistor, which is connected to the output diode and/or the input diode. The input diode and the output diode may be in the form of individual zones or in the form of individual zones or in the form of a common zone. The invention, which offers the advantage that the transport time through the connection independent of the length of the form of the connection, can be used, for example, in programmable filters, (de)multiplexers, (de)scramblers and the like.