Abstract: In a charge transfer device including spaced apart channels on a semiconductor substrate, first electrodes are disposed in gaps between the channels, second electrodes are disposed opposite alternate channels overlapping the adjacent first electrodes, and a third continuous electrode overlies the alternating channels and first and second electrodes in the charge transfer direction. A first clock phase is obtained by connecting alternate first electrodes with the adjacent second electrode in the direction of charge transfer, and a second clock phase is obtained by connecting the remaining first electrodes with the third electrode. The portion of the first electrode overlapped by the second electrode in the second clock phase is larger than that in the first clock phase for stable driving by first and second clock signals out of phase by 180.degree. and generated by a driver including a resonance circuit.

Abstract: An input protective apparatus for a semiconductor device (Q3) comprises an MOS transistor (Q4) having a thick gate insulating film formed therein. The MOS transistor (Q4) has one active layer connected to an input terminal (11) through a second resistor element (R2) and connected to a semiconductor device (Q3) to be protected through a first resistor element (R1), and an other active layer connected to a ground terminal. The input protective apparatus is adapted such that a resistance value R.sub.1 of a first resistor element (R1) and a resistance value R.sub.2 of the second resistor element (R2) satisfy the relation R.sub.1 >R.sub.2, and the on-resistance R.sub.3 of the MOS transistor (Q4) and the resistance value R.sub.2 satisfy the relation R.sub.3 <<R.sub.2.

Abstract: A heterojunction bipolar transistor includes an emitter layer of a first conductivity type, a base layer of a second conductivity type adjacent to the emitter layer, a collector buffer layer of the first conductivity type, and a collector layer arranged between the collector buffer layer and the base layer. The collector layer includes a first collector layer formed at the side of the base layer and a second collector layer arranged at the side of the collector buffer layer. The first collector layer is a semiconductor layer having an impurity concentration lower than that of the base layer. The second collector layer is a semiconductor layer of the second conductivity type having an impurity concentration higher than that of the first collector layer.

Abstract: A semiconductor circuit has a power source terminal set at a positive potential, a reference potential terminal set at a reference potential, a first MOS transistor whose current path is connected between the power source terminal and an output terminal, and a second MOS transistor whose current path is connected between the output terminal and the reference potential terminal. The gates of the first and second MOS transistors are commonly connected to an input terminal. The first and second MOS transistors are respectively n- and p-channel MOS transistors.

Abstract: A transistor cell (80) and enabling transistor (118) are provided. The transistor cell includes a trench transistor and a stacked transistor, with a cross-coupled capacitor between the gates of these transistors. The trench transistor includes a semiconductor region (98) functioning as a gate and first and second diffused regions (126, 135) as the source/drain regions therefor. The stacked transistor has a semiconductor layer (104) functioning as the gate and first and second doped regions (112, 114) within a semiconductor layer (110) functioning as the source/drain regions therefor. The stacked capacitor included herewith comprises semiconductor layer (104) and semiconductor region (98) having insulating layers (96, 102) therebetween.

Abstract: In a vertical field effect transistor including a source electrode and a gate on the front surface of a semiconductor substrate having one conductivity type and a drain electrode on the back surface of the substrate, the semiconductor device of the present invention has the structure wherein a connection region of one conductivity type positioned between two channel forming base regions of the opposite conductivity type is formed by a semiconductor layer having a higher impurity concentration than the drain region of the one conductivity type, and the surface portion of the connection region which is connected to the channel has a lower impurity concentration than the connection region.

Abstract: A class of intermetallic compound contact materials for III-V semiconductors is obtained by depositing successively and concurrently a thin film of a transition metal and a Group III metal upon the semiconductor and annealing the resultant structure, so resulting in the formation of a monocrystalline intermetallic contact. The contacts are stable at temperatures ranging from 600.degree.-900.degree. C. and may be fabricated by conventional vacuum deposition.

Abstract: A complementary NPN and PNP contactless vertical transistor structure is formed by a process that includes the steps of providing: (1) a buried layer and P- tub for NPN; (2) a channel stopper for NPN, and a buried layer for PNP; (3) isolation oxide for NPN and PNP; (4) a sink for NPN, and a ground for PNP; (5) a base for NPN, and a sink for PNP; (6) a base for PNP; (7) a N+ poly implant for NPN emitter and PNP extrinsic base; (8) a P+ poly implant for NPN extrinsic base and PNP emitter; (9) poly definition; (10) silicide exclusion for resistors and diodes; (11) contacts; (12) first metal; (13) vias; (14) second metal; and (15) scratch protection.

Abstract: An EEPROM constructed in accordance with our invention includes a voltage multiplier for generating an erase voltage and a voltage regulator circuit for controlling the magnitude of the erase voltage. The voltage regulator circuit includes a capacitive voltage divider for providing a first voltage proportional to the erase voltage, a reference voltage lead for providing a reference voltage and a control circuit for controlling the voltage multipler circuit so that if the first voltage is less than the reference voltage, the voltage multiplier circuit will increase the erase voltage, but if the first voltage is greater than the reference voltage, the voltage multiplier will not continue to increase the erase voltage. The voltage multiplier includes novel capacitors and transistors constructed using standard EEPROM processing to withstand high voltages without breaking down.

Abstract: A megabit dynamic random access memory realizing high integration and high reliability is disclosed. The need for an allowance for photomask alignment which is carried out to produce a stacked capacitor memory cell is eliminated. The plate electrode of each memory cell is isolated from the corresponding data line in a memory array by means of an insulating film which is self-alignedly provided around the plate electrode.

Abstract: The impurity concentration in a channel stopper in contact with a second fine active area is selected to be lower than the impurity concentration in a first active area that is wider than the second active area. This prevents the impurity concentration in the second active area from excessively rising that is caused by the diffusion of impurities when the insulating film for isolation is being formed, and helps improve characteristics and reliability of fine semiconductor device formed in the second active area.

Abstract: A dynamic memory cell comprises a storage transistor and an access transistor. The gate of the storage transistor is utilized as storage capacitor electrode, and is connected to its source by a high resistor. The drain of the storage is connected to a source of electrical potential (e.g., V.sub.CC). The access transistor connects the source of the storage transistor to a bit line. This arrangement multiplies the effective capacitance of the gate storage capacitor, reducing the area required and hence making the structure more compact than a typical inactive (one transistor) DRAM cell. In a preferred embodiment, the resistor is formed to overlie the storage transistor, and the drain of the storage transistor is connected to V.sub.CC by means of the sidewall of a trench formed in the semiconductor substrate.

Abstract: The invention relates to CCD Si detector configuration with a semiconductor sensibilizator. The spectral range of the detectors extends from 0.4 .mu.m to 1.6 .mu.m. The CCD Si detector configuration is produced as integrated structure so that a large picture element number can be achieved. The semiconductor layer sequence of the semiconductor sensibilizator is grown using differential molecular beam epitaxial growth techniques.

Abstract: This invention is related to a semiconductor light emitting device integrated with a Si-heat sink which contains not only a beam deflector but also the driving integrated circuits. A semiconductor light emitting device comprising a Si-substrate 2, V-groove 3 etched into substrate 2 and a beam deflector 9 on the wall of V-groove 3 wherein the transistor 22 for the driving and control on said Si-substrate is integrated so that light emitting device 1 and said integrated circuit are integrally mounted. The advantage of this invention is that the integration of the driving transistor with the light emitting device in the same package head reduces the packaging and bonding problems. Obtained is a compact optical system which easily radiates the heat dissipated by devices. This is in contrast to conventional light emitting devices which use the Si-substrate only as a mount and beam deflector.

Abstract: A Zener diode comprising a semiconductor substrate having an n-type region partly exposed at a main force of the substrate, a p.sup.+ -type region disposed contiguous to the n-type region and exposed at the main face of the semiconductor substrate, and an n.sup.+ -type region also exposed at the main face of the substrate and contiguously surrounded by the p.sup.+ -type region besides being contiguous to the p.sup.+ -type region. The arrangement of the semiconductor regions in relation to one another, and an an insulating layer on the main face of the substrate and to a pair of electrodes thereon, is such that the breakdown voltage is free from the influence of temperatures and of the ions contained in the insulating layer.

Abstract: A first charge storage electrode (21) has a first row (21b) of teeth interdigitated with a second row (22b) of teeth of a second charge storage electrode (22). The second storage electrode (22) has a third row (22c) of teeth interdigitated with a fourth row (23b) of teeth of a third charge storage electrode (23). The first and third rows (21b and 22c) overlie one group (11b) of a series of parallel conduction channels while the second and fourth rows (22b and 23b) overlie another group (11a) of the parallel channels. A first charge transfer electrode (24) is provided to transfer charge packets into sites beneath the first storage electrode.

Abstract: Base regions of first and second stage transistors are formed in a semiconductor substrate consisting of low and high resistivity collector layers, and emitter regions are formed in the respective base regions. The emitter region of the second stage transistor has an interdigital structure with a plurality of finger portions, and an emitter surface electrode is formed on the emitter region of the second stage transistor. The second stage transistor emitter surface electrode has an extending portion at a position spaced apart from a transistor operation region where the finger portions are formed. An emitter connection electrode is formed on the extending portion, and a lead is connected by soldering or the like to the emitter connection electrode.

Abstract: First to third N.sup.+ -type impurity regions are formed separately from one another by a preset distance in the surface area of a P-type semiconductor substrate or a P-well region formed in an N-type semiconductor substrate. The first impurity region is connected to a power source and the second impurity region is connected to a ground terminal. The third impurity region formed between the first and second impurity regions is connected to one end of an input protection resistor which is connected at the other end to a signal input pad.

Abstract: A collector contact (6) is fabricated which is attached on the side to the collector zone (1), and around which a moat (3) is produced which laterally restricts the collector zone (1). The depth of the moat (3) is so dimensioned to be at least equal to the vertical thickness of the collector zone (1). The collector contact (6) comprises a polycrystalline silicon layer which contains dopants of the same conductivity type as the collector zone (1), and covers a highly doped contacting zone (7') which has been diffused from the adjoining collector contact (6).

Abstract: A charge coupled device includes a plurality of first CCD shift-registers transferring charge signals in parallel and a second CCD shift-register receiving the charge signals from the first CCD shift-registers for a parallel-serial coversion, the second CCD shift-register being connected to the first CCD shift-registers through barrier regions covered with electrodes in the second CCD shift-register.