Abstract: A semiconductor device is primarily composed of a semiconductor substrate of a first conductivity type and a semidonductor layer of a second conductivity type formed in a principal plane of the semiconductor substrate. The device has both a bipolar transistor with the semiconductor layer itself being the collector region. The base region is of the first conductivity type and the emitter region is of the second conductivity type. Both regions are formed in the same layer as a JFET struture which includes the above collector region as channel a and the above base region as a gate. A semiconductor region of the first conductivity type is formed in the above semiconductor layer, the semiconductor layer itself, and the above base and emitter regions constitute a thyristor structure.

Abstract: A package for interconnecting a plurality of integrated circuit chips into a functional unit comprising a multilayer substrate having ground and power conducting layers and a frame for holding the chips with their terminal pads on the side of the frame opposite the substrate. Power and ground terminal pads on the chips are coupled to the appropriate potentials via registering conductive feedthroughs passing through the frame and into the substrate into contact with appropriate power or conductive layers in the substrate. Signal pads on the chips are interconnected by means of a conductive layer which is located over the chips on the side of the frame opposite the substrate.

Abstract: A Compact Reduced Parasitic Resonant Frequency Pulsed Power Source at Microwave Frequencies is disclosed which uses a series of stacked IMPATT diodes with thick metallic heat sinks interposed between each of the IMPATT diodes with the effective heat sink of each heat sink being roughly equivalent to the diode radius in length. The effective heat sink length is matched through the disclosed analysis to the effective heat sink of the base heat sink which is located at the bottom of the stack of IMPATT diodes. The diodes are operated in a pulsed fashion and the effective heat sink length is matched to the effective heat sink of the base heat sink that the temperature of the stacked IMPATT diodes track together in time.

Abstract: A protective circuit consisting of a resistor and MOSFET in a diode form and a switching element are connected to a bonding pad in order to prevent destruction of an internal circuit consisting of one or more MOSFETs. The switching element may consist of a parasitic MOSFET whose source and drain regions are formed by well regions. One of the well regions is connected to a semiconductor region as a guard ring.

Abstract: This protected MOS transistor circuit has a p-type semiconductor substrate, VSS terminal, input MOS transistor, first resistor connected to the gate electrode of transistor, and MOS transistor which has a gate electrode connected to the VSS terminal and a current path connected between the VSS terminal and a junction of the first resistor and the gate electrode of the input MOS transistor. This protected MOS transistor circuit further has a second resistor connected in series with the first resistor, and pn-junction diode connected reversely between the VSS terminal and the junction of the first and second resistors.

Abstract: An integrated circuit is disclosed in which a plurality of semiconductor substrates are stacked in such a manner that an insulating board, provided with (1) structure, such as grooves, for transmitting a coolant so as to dissipate heat, and (2) an electrical interconnection member for electrically connecting adjacent semiconductor substrates, is sandwiched between semiconductor substrates. In order to attain the high-speed signal transmission between a semiconductor substrate and an insulating board, a signal current flows not only in a main surface of the semiconductor substrate but also in directions perpendicular to the main surface. The insulating board may be formed of an insulating silicon carbide plate which has a plurality of grooves filled with a metal.

Abstract: A buried contact structure to decrease the spreading resistance of various circuit elements of semiconductor devices such as transistors and for reducing the resistance of polysilicon wires typically used in short lengths to connect the circuit elements to other metallic wires. The buried contact structure more specifically includes a phosphorous diffusion superimposed on the field implant which includes the source and/or drain of the transistor device. An overlayed layer of polysilicon is then disposed to make contact with the buried contact diffusion. The field implant used for the source and drain may, for example, be boron. The buried contact structure has a lower resistance than the field implant and therefore provides a lower resistance path for the device current.

Abstract: A metal-oxide-semiconductor (MOS) field effect transistor comprises monocrystalline, doped silicon zones which are formed between gate electrodes and the field oxide zones by selective epitaxy and which simultaneously serve as diffusion sources for the formation of source and drain zones in the substrate and as terminal zones for silicide source and drain terminals. This terminal technology serves to form particularly planar structures, with a high integration density, which structures are characterized by reduced drain field strength, low series resistances and a small danger of substrate short circuits. Processes for the formation of this structure in CMOS circuits are simple to perform. The present invention can be applied to all NMOS, PMOS and CMOS circuits.

Abstract: A MIS semiconductor device comprises a crystalline substrate having a first energy band gap and a crystalline passivation layer overlying a surface of the substrate. The passivation layer is comprised of a semiconductor material having a wider band gap than the semiconductor material of the substrate. In an illustrative embodiment of the invention a MIS semiconductor device comprises a mercury-cadmium-telluride (HgCdTe) substrate having a cadmium-telluride (CdTe) heterojunction formed thereon, the CdTe functioning as a layer of high-quality passivation. A metal gate insulator may be SiO.sub.2, low temperature CVD Si.sub.3 N.sub.4, or any other suitable insulator deposited at a relatively low temperature.

Abstract: A charge-coupled device comprising two clock electrodes (4,5) on the two opposite sides of the charge transport channel (3) and which extend the entire length of the channel. Charge storage regions (6-9) are located zigzagwise on both sides of the channel, as a result of which during charge transport the charge is transferred from one side to the other. Due to the separation of the electrodes the parasitic capacitance between them is low, achieving low power dissipation. The electrodes are located in grooves at the sides of the channel, leaving the surface of the channel unobstructed. The device can therefore serve as an image sensor of high sensitivity.

Abstract: A one-piece interconnection structure (10) for an SO package (60) is formed from a single sheet strip (12) of copper having a thickness of about 8 mils. Contact finger patterns (14) are formed from a plurality of contact fingers (22) which extend in cantilever fashion. The fingers (22) have tips (24) of a reduced thickness of between about 2-3 mils. Stress relief slots (26) having a depth of about 2 mils are formed in the underside of each finger (22) spaced back from the tips (24) to give the fingers increased flexibility for downward bending during assembly operations. Vertical slots (28) on opposing sides of the fingers behind the stress relief slots give increased lateral flexibility to the fingers. Steps (30) extend vertically along the lateral fingers (22) and have two surfaces (32 and 34) angularly disposed with respect to central surface (36) on the top and bottom fingers.

Abstract: Dynamic RAM having memory cells, each of the memory cells having a capacitor with the electrode comprised of a first semiconductor region of a first type of conductivity formed in a substrate of second conductivity type. The first semiconductor region is formed by introducing impurities using a mask comprising (1) a nitride film which is deposited so as to define part of the shape of the capacitor. An oxide film, formed by thermal oxidation of the substrate, defines the shape of the memory cells, and each of the memory cells further have at least a second semiconductor region of a second type of conductivity formed between and under the electrodes, the shape thereof being defined by the nitride film and the oxide film that is formed by thermal oxidation.

Abstract: A gate turn-off (GTO) thyristor has a plurality of unit GTO thyristors of strip-like configuration in a same semiconductor substrate, each unit GTO thyristor being constructed of an N emitter layer, P base layer, N base layer and P emitter layer. The P base and N base layers are shared in common for all the unit GTO thyristors which are formed in a multi-ring configuration. The exposed area of the P emitter layer of a unit GTO thyristor located far from the gate signal input area is made smaller than that of the P emitter layer of a unit GTO thyristor located relatively closer to the gate signal input area.

Abstract: A sense transistor of an EEPROM has a conductive diffusion layer which is isolated from the source-drain region of the sense transistor and newly formed on the surface of the semiconductor substrate beneath the floating gate of the sense transistor. The conductive diffusion layer is connected to the control gate of the sense transistor, whereby a capacitance between the control gate and the floating gate is increased without increasing the facing area of the control gate and the floating gate.

Abstract: A charge transfer device (CTD) eliminating the background level of a detected signal provided with an input circuit comprising an injection source (12) and an electrode (16) controlling a storage potential well, which can be subdivided into an evacuation well (18) and an output well (19) separated by the separation potential produced by a separation electrode (27). This CTD is characterized in that its input circuit comprises a floating electrode (25) connected to the separation electrode (27) in order that the separation potential controls the background level and an insulation electrode (28) insulating the reference well (29) from the output well (19), during the measuring operations, the respective dopings under the floating electrode and under the separation electrode being obtained in order that the potential wells situated under each of these respective electrodes have different depths.

Abstract: The present invention relates to a semiconductor device manufactured by removing a part of a semiconductor layer containing an amorphous semiconductor and which is formed over separate electrodes existing on the same substrate and characterized in that the mean oxygen content of the portion of the semiconductor adjacent the removed portion and 10 .mu.m inward is in a range of 0.5-10 atom %, and to a manufacturing method for the semiconductor device characterized in that the semiconductor layer is removed partly in an oxidative environment by the use of laser ray means. The invention provides semiconductor devices diminished in leak current.

Abstract: An isolation structure for isolating a pilot device from the main device of a monolithic semiconductor device. The isolation structure comprises a pair of spaced isolation channels separating the pilot device from the main device. An electrode insulatively disposed over the region between the two isolation channels is shorted by a metallization layer to the isolation channel closest to the pilot device. In this manner, parasitic transistor turn on of the isolation structure is prevented.

Abstract: In a semiconductor IC, a diode and a resistor for surge protection are integratedly formed in a p-type common island region laterally isolated from a p-type epitaxial layer by oxide film, by forming an n-type region of high impurity concentration to reach down to an n-type buried region and a resistor region, respectively; the IC has higher integration and larger junction area of the diode, and achieve better surge protection.

Abstract: A semiconductor imaging device includes lateral MOS static induction transistors including: a semiconductor layer formed on an insulating substrate or a high-resistance semiconductor substrate; and picture elements arranged in the form of a matrix over the surface of the semiconductor layer, the picture elements respectively constituted by lateral MOS static induction transistors each having a source region and a drain region both of which serve as main electrodes and a gate region for storing therein a photoelectric signal. Isolating regions are formed between the respective picture elements vertically or laterally on the matrix so that the picture elements which are adjacent to each other vertically or laterally share their source and drain regions with each other. Accordingly, each of the gate regions constitutes in combination with the adjacent source or drain region an equivalent unit picture element, thereby improving the density of picture-element formation.

Abstract: The invention comprises a Schottky barrier type infrared photodetector which is monolithically integrated on a silicon waveguide. A Schottky barrier contact is positioned directly on a silicon waveguide to absorb grazing incidence optical signals passing through the waveguide. The Schottky contact is operated in the avalanche or reverse bias mode to generate a useable electrical signal.