Abstract: Monolithically integrated waveguide-photodiode-FET combination comprising waveguide layer (2), photodiode layer (3), FET layer (4) and a common cover layer (5) applied on a carrier substrate (1) of III-V semiconductor material, having butt coupling between waveguide layer (2) and photodiode layer (3), having introduced dopings for fashioning photodiodes and FETs and having a parting region (19) for the limitation of photodiodes and FETs.

Abstract: A semiconductor integrated circuit device having multilayer power supply lines includes a plurality of power supply lines formed on a semiconductor chip for supplying power to the cells. The power supply lines are constructed by the multilayer structure having three different layer levels. First-level (lower) and third-level (upper) power supply lines are arranged in parallel so as to overlap each other. Second-level (intermittent) power supply lines are arranged in parallel so as to extend in a direction perpendicular to the first-level and third-level power supply lines. The overlapping first and third power supply lines are set at different potentials.

Abstract: A dielectrically-isolated structure and method of fabricating the same is disclosed wherein the structure includes a layer of silicide which is selectively doped, preferably using an ion implantation process. The doped silicide is then used as the diffusion source for the subsequent formation (through a heat treatment) of various active portions (collector, emitter, drain, source, for example) of a variety of high-voltage, high-speed active devices. The non-doped silicide is advantageously utilized as a low-resistance contact between the buried diffusion region and the surface electrode.

Abstract: A device having high temperature operating characteristics is provided by depositing n-type cubic gallium nitride on n-type cubic silicon carbide to provide an ohmic contact or electrode. High temperature operating characteristics are also provided in a device having a pn heterojunction between a layer of cubic p-type silicon carbide or gallium arsenide and a first layer of cubic n-type gallium nitride. In a power transistor, a second layer of n-type gallium nitride is deposited on the other surface of the silicon carbide or gallium arsenide to form a pn heterojunction. The gallium nitride layer that is connected as an emitter is forward biased to cause electron injection into the silicon carbide or gallium arsenide layer. In a phototransistor device having high temperature operating characteristics, a transparent layer of cubic n-type gallium nitride is deposited on each side of either cubic p-type silicon carbide or gallium arsenide.

Abstract: A semiconductor device having a plurality of conductive layers is disclosed. The device has first level conductors (9) formed spaced apart on a semiconductor substrate (1). The semiconductor substrate (1) is provided with impurity diffusion regions (11) in its major surface between adjacent first level conductors (9). A triple layer insulation formed of a pair of oxide layers (12, 14) and an silicon oxide layer (13) sandwiched between the oxide layers (12, 14) covers the semiconductor substrate (1) and the first level conductors (9) thereon. At least one contact hole (15) is formed to extend through the triple layer insulation to either the impurity diffusion region (11) in the semiconductor substrate (1) or the first level conductor (9) on the semiconductor substrate (1). A second level conductor (16, 17) is provided on the triple layer insulation and on the inner surrounding wall of the contact hole (15).

Abstract: A solid state imager device having a semiconductor substrate which includes a substrate region of a first conductivity type, a light receiving area of a second conductivity type forming a light receiving section, a charge transfer section and a low impurity concentration region arranged under and contacting with the light receiving area and between the light receiving area and the substrate region, a forward electrode formed on the semiconductor substrate through a dielectric layer, and a charge transfer control electrode formed on the dielectric layer between the light receiving section and the charge transfer section, wherein the forward electrode is supplied with a voltage for forming a charge storage layer on a boundary plane between the dielectric layer and the forward electrode, and the edge of the transfer control electrode at the side of the light receiving area substantially coincides with the edge of the light receiving area at a side facing to the charge transfer section.

Abstract: An avalanche photodiode comprises an electron multiplication layer of superlattice including InAlAs mixed crystal layers which are lattice-matched with InP, and InGaAsP mixed crystal which are lattice-matched with InP and are provided with a bandgap energy of 1.0 eV to 1.2 eV at the room temperature. In the electron multiplication, a conduction band discontinuity is much greater than a valence band discontinuity to increase a ratio between ion densities .alpha. and .beta. for electron and hole, so that a noise level is decreased and a response characteristic is improved.

Abstract: A dynamic random access memory device including one-transistor type memory cells each having a trench capacitor is disclosed. An impurity region of a conductivity type opposite to the substrate and having a net-like plane shape is provided in an inner portion of the substrate, and the impurity region is led-out at a part to the major surface of the substrate. A trench is formed in the substrate from the major surface into the impurity region so that a wall section of the trench is constituted by the impurity region. A dielectric film of the capacitor is formed on the wall section, and a capacitor electrode is formed on the dielectric film and connected to source or drain region of the transistor.

Abstract: A serial-parallel-serial, charged-coupled device includes an array of horizontal rows and columns of closely spaced charge storage cells. Each storage cell is formed by an electrode covering an insulation layer above a semiconductor substrate. The semiconductor substrate of each storage cell includes a channel region for conducting carriers laterally through the storage cell. The channel region of each storage cell included both in a first row of the array and in any column of the array has a tilted potential gradient providing an electric field facilitating charge carrier drift within the channel region in two lateral directions, toward a neighboring storage cell of the first row and also toward a neighboring storage cell of its column.

Abstract: A photoelectric conversion apparatus in which a plurality of photoelectric conversion elements are arranged in an array, and the outputs of the photoelectric conversion elements are read. The apparatus includes a plurality of switching elements connected equivalently in parallel with the respective photoelectric conversion elements. The photoelectric conversion elements of a particular row or column are connected in series.

Abstract: A self-aligned TFT array for liquid-crystal display devices and a method of manufacturing the array are disclosed. A protective insulating layer on a semiconductor layer is exactly aligned with a gate electrode. A self-alignment method is used for patterning the protective insulating layer and an impurity-doped semiconductor layer on the semiconductor layer. No lift-off process is necessary.

Abstract: An infrared imager (10) is disclosed for sensing infrared radiation. The imager (10) comprises a detection layer (14) of semiconductor material which is operable to detect the occurrence of infrared radiation and generate free charge carriers in response thereto. The imager (10) also includes a transfer layer (16) which is operable to generate a signal in response to the free charge carriers infrared radiation generated by the detection layer (14) and deliver the signal to the output of the imager (10). An electropotential barrier (18) is located within the imager (10) to selectively restrict migration of free charge carriers from the detection layer (14) to the transfer layer (16). The imager (10) includes a buried channel (49) and is capable of two color operation.

Abstract: An interferometer comprises an optical system for generating an interference pattern of a predetermined configuration in a focal plane of the interferometer, and a detector device for measuring the distribution of optical power over the focal plane. The detector device comprises a body of semiconductor material having first and second opposite main surfaces, one of which surfaces lies substantially in the focal plane of the interferometer. The body of semiconductor material has a region of a first conductivity type and a channel of a second, opposite conductivity type at the first surface thereof and bounded by the region of the first conductivity type. The configuration of the channel conforms substantially to the predetermined configuration of the interference pattern. The semiconductor material responds to electromagnetic radiation in a given spectral region by generating charge carriers. Charge carriers that are created in or diffuse into the channel are confined in the channel.

Abstract: The semiconductor devices include a semiconductor substrate, a first CCD region formed at the surface of said substrate, and a second CCD region having a side connected to said first CCD. A channel region of the first CCD region has a different channel potential at a latter part of the end transfer electrode corresponding to the portion of the first CCD region connected to the second CCD region.

Abstract: A semiconductor device, CHARACTERIZED in that a Darlington transistor in which in one surface of a semiconductor of a first conductivity type, base regions of a second conductivity type, the number of which is larger that the number of base-emitter junctions of the transistor, are formed, emitter regions of the first conductivity type are formed in the base regions, respectively, and base electrodes and emitter electrodes are connected to the base regions and emitter regions, respectively, and are further connected in such a manner that the base electrode of a base region is connected to the emitter electrode in the next base region, is the same in conductivity type arrangement as the transistor and is mounted on the same substrate as the transistor in such a manner that the Darlington transistor is insulated from the transistor, and the base electrode of the transistor is connected to the collector electrode of the Darlington transistor which is formed on the other surface of the semiconductor and to the bas

Abstract: A source electrode and a drain electrode are formed apart on an insulating substrate, and a semiconductor layer is formed on the substrate between the source and drain electrodes. An insulating organic molecular film is formed all over the source and drain electrodes and the semiconductor layer. Ions are implanted into a selected top surface region of the insulating organic molecular film, corresponding to the semiconductor layer, by which chains of molecules in the surface region are cut to form free carbon, providing a conductive gate electrode.

Abstract: A semiconductor device in which, in a planar type bipolar transistor having a collector layer (22) in a substrate side, a base layer (23) formed on the collector layer (22) and an emitter island (24) formed in the base layer (23), a groove (25) is provided in the emitter island (24) to reach at least the interface between the base layer (23) and the collector layer (22) to form a conductive film (27) through a dielectric film (26) in the groove to be employed as a gate electrode of a MOS-FET thereby to implement a monolithic parallel Bi-MOS device, while the base electrode (28) of the bipolar transistor (40) and the gate electrode (29) of the MOS-FET (50) are connected with a help of diodes including a zener diode (10) thereby to implement a monolithic three-terminal parallel Bi-MOS switching device of small chip size.

Abstract: A charge transfer device, suitable for use, for example, in a solid state imager device, having a floating gate electrode in a charge detecting section, a protruding portion provided in at least one of the floating gate electrodes or a gate electrode arranged adjacent to the floating gate electrode, wherein the floating gate electrode and the gate electrode arranged adjacent to the floating gate electrode overlap each other at the protruding portion within an insulating layer, and whereby the parasitic capacitance associated with the floating gate electrode is decreased and the charge voltage converting gain is increased, rendering it possible to obtain an image signal with a good signal/noise ratio, when the charge transfer device is used for a solid state imager device.

Abstract: The invention relates to a charge transfer device (CTD) having two or four phases, for which the speed of transferring the stored charges is increased by means of self-induction members connected to each of the clock areas of each memory element so that the capacitive impedance presented initially to the clock signal generator by the CTD becomes a substantially resistive impedance. Such a charge transfer device having an increased transfer speed is used in digital oscilloscopy or in systems for handling pictures.

Abstract: A semiconductor optical device in which a hetero-structure is constructed by sandwiching a semiconductor layer including a thin film made of a semiconductor or insulator between semiconductors having a larger band gap than that of the thin film so that the electron-hole pairs generated through the thin film may recombine by the tunnel effect to emit an optical beam. The optical device is equipped with electrodes for controlling the probability of said recombination.