Patents Examined by Nicole Barreca
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Patent number: 7105279Abstract: During the patterning of a semiconductor layer, an N-free SiOx layer is produced under an acid-forming photoresist layer in order to prevent a resist degradation. The Si content of the grown SiOx layer being varied in order to set a desired extinction coefficient k and a desired refractive index n. The SiOx layer formation is effected by a vapor phase deposition, SiH4 and O2 being used as starting gases.Type: GrantFiled: April 28, 2003Date of Patent: September 12, 2006Assignee: Infineon Technologies AGInventors: Mirko Vogt, Alexander Hausmann
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Patent number: 7094521Abstract: After forming a resist film made from a chemically amplified resist material, pattern exposure is carried out by irradiating the resist film with exposing light while supplying, between a projection lens and the resist film, a solution of water (having a refractive index of 1.44) that includes an antifoaming agent and is circulated and temporarily stored in a solution storage. After the pattern exposure, the resist film is subjected to post-exposure bake, and the resultant resist film is developed with an alkaline developer. Thus, a resist pattern made of an unexposed portion of the resist film can be formed in a good shape.Type: GrantFiled: August 14, 2003Date of Patent: August 22, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masayuki Endo, Masaru Sasago
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Patent number: 7090966Abstract: A process of providing a hydrophobic property to the surface of a plate, and a process of providing a hydrophilic property to the surface by irradiating energy light (radiation) on the surface of the plate, which is provided with the hydrophobic property are provided. Variations in the accumulated illumination intensity of radiation on the surface of the plate are controlled to 20% or less.Type: GrantFiled: March 25, 2004Date of Patent: August 15, 2006Assignee: Seiko Epson CorporationInventors: Toshimitsu Hirai, Hironori Hasei
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Patent number: 7090965Abstract: A method for enhancing adhesion between a reworked photoresist and an underlying oxynitride film. A photoresist pattern layer is formed on an oxynitride layer overlying a substrate. The photoresist pattern layer is removed by acidic solution or oxygen-containing plasma. A surface treatment is performed on the oxynitride layer using a development solution to repair the damaged oxynitride layer due to removing the overlying photoresist pattern layer. A reworked photoresist pattern layer is formed on the oxynitride layer.Type: GrantFiled: July 1, 2003Date of Patent: August 15, 2006Assignee: Nanya Technology CorporationInventors: Wen-Bin Wu, Yuan-Shan Wu, Yi-Nan Chen, Teng-Yen Huang
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Patent number: 7087363Abstract: A method of forming a top gate thin film transistor (TFT). By performing photolithography using a first reticle, a photoresist layer having a thick photoresist layer portion and a thin photoresist layer portion is formed on a silicon layer in an active area. Thus, a channel layer and source/drain regions in a silicon island are defined by the same patterning process. In addition, a gate and an LDD region in the silicon island are defined by photolithography using a second reticle and a backside exposure process. Accordingly, the top gate TFT fabrication process of the present invention requires only two reticles, and thereby reduces costs.Type: GrantFiled: August 29, 2003Date of Patent: August 8, 2006Assignee: Industrial Technology Research InstituteInventors: Chih-Chiang Chen, Ching-Sang Chuang, Jiun-Jye Chang
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Patent number: 7083903Abstract: Methods of etching a carbon-rich layer on organic photoresist overlying an inorganic layer can utilize a process gas including CxHyFz, where y?x and z?0, and one or more optional components to generate a plasma effective to etch the carbon-rich layer with low removal of the inorganic layer. The carbon-rich layer can be removed in the same processing chamber, or alternatively can be removed in a different processing chamber, as used to remove the bulk photoresist.Type: GrantFiled: June 17, 2003Date of Patent: August 1, 2006Assignee: Lam Research CorporationInventors: Erik A. Edelberg, Robert P. Chebi, Gladys Sowan Lo
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Patent number: 7083899Abstract: Disclosed is a method for manufacturing a semiconductor device by employing a dual damascene process. After a first insulation film including a conductive pattern is formed on a substrate, at least one etch stop film and at least one insulation film are alternatively formed on the first insulation film. A via hole for a contact or a trench for a metal wiring is formed through the insulation film, and then the via hole or the trench is filled with a filling film including a water-soluble polymer. After a photoresist film is coated on the filling film, the photoresist film is patterned to form a photoresist pattern and to remove the filling film. The DOF and processing margin of the photolithography process for forming the photoresist pattern can be improved because the photoresist film can have greatly reduced thickness due to the filling film.Type: GrantFiled: May 5, 2003Date of Patent: August 1, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-Cheol Kim, Dae-Youp Lee
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Patent number: 7078160Abstract: A method of protecting a sensitive layer from harsh chemistries. The method includes forming a first sensitive layer, forming a second layer upon the first layer, then forming a third layer over the second layer. The third layer is utilized as a mask during patterning of the second layer. During patterning, however, the second layer is only partially etched, thus leaving a buffer layer overlying the first layer. The third layer is completely removed while the buffer layer protects the first layer from the harsh chemicals that are utilized to remove the third layer. Then, the buffer layer is carefully removed down to the surface of the first layer.Type: GrantFiled: June 26, 2003Date of Patent: July 18, 2006Assignee: Intel CorporationInventors: Justin K. Brask, Bruce A. Block, Uday Shah
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Patent number: 7070914Abstract: Disclosed is a process for forming an image on a substrate, comprising the steps of: (a) coating on the substrate a first layer of a radiation sensitive, antireflective composition; (b) coating a second layer of a photoresist composition onto the first layer of the antireflective composition; (c) selectively exposing the coated substrate from step (b) to actinic radiation; and (d) developing the exposed coated substrate from step (c) to form an image; wherein both the photoresist composition and the antireflective composition are exposed in step (c); both are developed in step (d) using a single developer; wherein the antireflective composition of step (a) is a first minimum bottom antireflective coating (B.A.R.C.) composition, having a solids content of up to about 8% solids, and a maximum coating thickness of the coated substrate of ? 2 ? n wherein ? is the wavelength of the actinic radiation of step (c) and n is the refractive index of the B.A.R.C. composition.Type: GrantFiled: January 9, 2002Date of Patent: July 4, 2006Assignee: AZ Electronic Materials USA Corp.Inventors: Mark O. Neisser, Joseph E. Oberlander, Medhat A. Toukhy, Raj Sakamuri, Shuji Ding-Lee
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Patent number: 7070911Abstract: A structure and method for reducing standing waves in a photoresist during manufacturing of a semiconductor is presented. Embodiments of the present invention include a method for reducing standing wave formation in a photoresist during manufacturing a semiconductor device comprising depositing a first anti-reflective coating having an extinction coefficient above a material, and depositing a second anti-reflective coating having an extinction coefficient above the first anti-reflective coating, such that the first anti-reflective coating and the second anti-reflective coating reduce the formation of standing waves in a photoresist during a lithography process.Type: GrantFiled: January 23, 2003Date of Patent: July 4, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Dawn Hopper, Kouros Ghandehari, Minh Van Ngo
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Patent number: 7067237Abstract: Disclosed herein are a method for forming a pattern of a one-dimensional nanostructure, and a pattern of a one-dimensional nanostructure formed by the method. The method comprises the steps of (i) coating a photocatalytic compound onto a substrate to form a photocatalytic film, and selectively exposing the photocatalytic film to light to form latent image centers for crystal growth, (ii) growing metal crystals by plating the latent pattern to form a metal pattern, and (iii) selectively growing a one-dimensional nanostructure on the metal pattern acting as a catalyst.Type: GrantFiled: June 28, 2004Date of Patent: June 27, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Jin Young Kim, Chang Ho Noh, Euk Che Hwang
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Patent number: 7067235Abstract: A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist layer over the non-silicon containing photoresist layer; exposing an exposure surface of the silicon containing photoresist layer to an activating light source said exposure surface defined by an overlying pattern according to a photolithographic process; developing the silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least nitrogen and oxygen.Type: GrantFiled: January 15, 2002Date of Patent: June 27, 2006Inventors: Ming Huan Tsai, Hun-Jan Tao
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Patent number: 7067241Abstract: A method for producing a unit having a three-dimensional surface patterning on a base layer. A photoresist is applied to a base layer and subjected to a masked exposure matched to a predetermined final surface patterning. Parts of the photoresist layer are removed by developing to provide an initial surface patterning, including photoresist sacrificial subregions. A coating which covers the initial surface patterning is then applied. Energy is then applied to the initial surface patterning to destabilize the sacrificial layer regions. The initial surface patterning is acted on by a high-pressure liquid jet at a predetermined treatment temperature such that at least part of the coating which covers the sacrificial layer regions are mechanically removed or at least broken open to produce the final surface patterning. The liquid has a negligible chemical reaction rate and/or physical dissolution rate with respect to materials of the unit and/or organic fluid-sealing means.Type: GrantFiled: May 5, 2003Date of Patent: June 27, 2006Assignee: Unaxis Balzers AktiengesellschaftInventors: Patrick Grabher, Claus Heine-Kempkens, Roger Bischofberger
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Patent number: 7063938Abstract: A method of preparing patterned colloidal crystals includes filling a monomer solution in the interstices between particles of planar colloidal crystals for photopolymerization inside them, and performing a selective photopolymerization process between the colloidal crystals using a mask. In one exemplary method, a first monomer solution for photopolymerization is filled inside planar colloidal crystals. A first selective photopolymerization process is performed inside the colloidal crystals using a mask. A second monomer solution for photopolymerization is filled into the firstly patterned colloidal crystals. At least one additional photopolymerization process is performed inside the firstly patterned colloidal crystals using an additional mask. Through this method, colloidal crystalline regions oriented in the same direction with different refractive indexes can be controlled in a level of ?m. Further, repeated patterns can be inexpensively and easily prepared.Type: GrantFiled: September 12, 2003Date of Patent: June 20, 2006Assignee: Korea Advanced Institute of Science and TechnologyInventors: Seung-Man Yang, Ki-Ra Yi, Yong- Hak Park, Sarah Kim
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Patent number: 7060418Abstract: In a method for the manufacture of a printed circuit on a dielectric carrier (2), in a first step a circuit pattern (1) is applied with an electrically conductive ink and, in a second step, the circuit model is plated, the electrically conductive ink being applied by means of a method of gravure printing and the plating being done by electrolytic or chemical means.Type: GrantFiled: May 23, 2002Date of Patent: June 13, 2006Assignee: FCIInventor: Christophe Mathieu
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Patent number: 7060421Abstract: Conductive tracks disposed on an electrically non-conductive support material by depositing a metallized layer on metal nuclei produced by using electromagnetic radiation to break up electrically non-conductive metal compounds dispersed in the support material, and a method for producing them. The electrically non-conductive metal compounds are insoluble spinel-based inorganic oxides which are thermally stable and are stable in acidic or alkaline metallization baths, and which are higher oxides with a spinel structure, and which remain unchanged in non-irradiated areas. The spinel-based inorganic oxides used are heat resistant and remain stable after being subjected to soldering temperatures. The conductor tracks are reliably and easily produced and adhere strongly to the support.Type: GrantFiled: January 5, 2004Date of Patent: June 13, 2006Assignee: LPKF Laser & Electronics AGInventors: Gerhard Naundorf, Horst Wissbrock
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Patent number: 7056648Abstract: Copper and copper alloys are etched to provide uniform and smooth surface by employing an aqueous composition that comprises an oxidant, a mixture of at least one weak complexant and at least one strong complexant for the copper or copper alloy, and water and has a pH of about 6 to about 12 so as to form an oxidized etch controlling layer and to uniformly remove the copper or copper alloy; and then removing the oxidized etch controlling layer with a non-oxidizing composition. Copper and copper alloy structure, having smooth upper surfaces are also provided.Type: GrantFiled: September 17, 2003Date of Patent: June 6, 2006Assignee: International Business Machines CorporationInventors: Emanuel Cooper, Bruce Furman, David Rath
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Patent number: 7052825Abstract: A substrate includes fine lines. The fine lines are obtained according to a fine-line forming process, which includes a process of projecting light from above the substrate onto predetermined regions on a photosensitive material provided on the substrate and a developing process after the light projection process. A narrow-width portion is provided at an end portion of each of the fine lines in a longitudinal direction of the fine line. The width of the narrow-width portion is smaller than the width of a portion adjacent to the narrow-width portion.Type: GrantFiled: February 20, 2004Date of Patent: May 30, 2006Assignee: Canon Kabushiki KaishaInventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
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Patent number: 7049052Abstract: A method for etching a feature in a layer is provided. An underlayer of a polymer material is formed over the layer. A top image layer is formed over the underlayer. The top image layer is exposed to patterned radiation. A pattern is developed in the top image layer. The pattern is transferred from the top image layer to the underlayer with a reducing dry etch. The layer is etched through the underlayer, where the top image layer is completely removed and the underlayer is used as a pattern mask during the etching the layer to transfer the pattern from the underlayer to the layer.Type: GrantFiled: May 9, 2003Date of Patent: May 23, 2006Assignee: Lam Research CorporationInventors: Hanzhong Xiao, Helen H. Zhu, Kuo-Lung Tang, S. M. Reza Sadjadi
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Patent number: 7041434Abstract: In an improved technique for adjusting an etch time of a resist trim process, additional measurement data representing an optical characteristic, such as the reflectivity of an anti-reflective coating, is used. Since the initial thickness of the resist mask features may significantly depend on the optical characteristics of the anti-reflective coating, the additional measurement data allow compensation for process variations more efficiently as compared to the conventional approach.Type: GrantFiled: March 30, 2004Date of Patent: May 9, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Jan Raebiger, André Holfeld