Patents Examined by Nicole Barreca
-
Patent number: 7041433Abstract: The invention relates to a flat coil and to a lthographic method for producing microcomponents with metal component sources in the sub-millimeter range. According to the inventive method, a resist material is structured by means of selective exposition and removing the unexposed zones and filling in the gaps between the resist structures with metal by means of a galvanic method to produe the metal component structures. The aim of the invention is to improve such a method so that the microcomponents can be subdivided during said process. To this end, a structured three-dimensional sacrificial metal layer is produced during the production of the microcomponent, said sacrificial layer delimiting the microcomponent and being removed once the microcomponent is due to be subdivided.Type: GrantFiled: November 17, 2000Date of Patent: May 9, 2006Assignee: Institut fur Mikrotechnik Mainz GmbHInventors: Felix Schmitz, Matthias Nienhaus, Manfred Lacher
-
Patent number: 7029821Abstract: Methods are provides methods are provided to prepare photoresist and organic antireflective coating composition with a filter having a mean pore size of less than about 0.4 microns. Photoresist compositions and antireflective coatings produced by such methods can provide manufactured microelectronic devices that have significantly reduced defects. Photoresist and antireflective compositions obtainable by such methods also are provided.Type: GrantFiled: February 11, 2004Date of Patent: April 18, 2006Assignee: Rohm and Haas Electronic Materials LLCInventors: Richard J. Carey, Peter Trefonas, III, Michael J. Kaufman
-
Patent number: 7026101Abstract: Antireflective compositions are provided that contain a basic additive material. Such use of a basic material can significantly decrease or even completely eliminate notching of an overcoated photoresist relief image. Antireflective formulations of the invention are preferably crosslinking compositions and may contain a resin component in addition to the basic additive. Antireflective compositions of the invention can be effectively used at a variety of wavelengths used to expose an overcoated photoresist layer, including 248 nm and 193 nm.Type: GrantFiled: July 30, 2001Date of Patent: April 11, 2006Assignee: Shipley Company, LLCInventors: Peter Trefonas, III, Manuel doCanto, Edward K. Pavelchek
-
Patent number: 7026102Abstract: A selective wetting material is formed by plasma depositing a film on a substrate from a two-component reaction of a silicon donor and organic precursor, and photo-oxidizing selected regions of the deposited film to form wetting regions to which a liquid will selectively adhere. When the liquid is an electrically conductive material, the process may be used to form printed circuits on a circuit board. When the substrate is optically transparent and the non-photo-oxidized regions of the film are removed, the process may be used to form a photomask.Type: GrantFiled: April 24, 2004Date of Patent: April 11, 2006Inventor: Ronald M. Kubacki
-
Patent number: 7022464Abstract: An integral plated resistor having an improved range of resistance is produced by uniformly dispersing an effective amount of various particles in an electroless nickel phosphorus plating composition so that the particles are codeposited with the electroless nickel phosphorus plating composition. Preferred particles include, polytetrafluoroethylene, silicon carbide, tungsten carbide, and other particles that fully sinter at a temperature of less than about 170° C. The improved nickel phosphorus plated resistors of the invention demonstrate increased stability during manufacturing press cycles and a greater range of resistance values than have previously been achieved.Type: GrantFiled: August 25, 2004Date of Patent: April 4, 2006Inventors: Peter Kukanskis, Steven Castaldi
-
Patent number: 7022440Abstract: A device pattern of a semiconductor device. The pattern is defined by a plurality of non-straight lines that are inwardly arched and are formed from plural segments of plural ellipses that are arranged to surround the pattern.Type: GrantFiled: September 13, 2004Date of Patent: April 4, 2006Assignee: NEC Electronics CorporationInventor: Mami Takeuchi
-
Patent number: 7018781Abstract: Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.Type: GrantFiled: March 29, 2004Date of Patent: March 28, 2006Assignee: Infineon Technologies, AGInventors: Hans-Georg Fröhlich, Oliver Genz, Werner Graf, Stefan Gruss, Matthias Handke, Percy Heger, Lars Heineck, Antje Laessig, Alexander Reb, Kristin Schupke, Momtchil Stavrev, Mirko Vogt
-
Patent number: 7018779Abstract: A process for prohibiting amino group transport from the top surface of a layered semiconductor wafer to a photoresist layer introduces a thin film oxynitride over the silicon nitride layer using a high temperature step of nitrous oxide (N2O) plus oxygen (O2) at approximately 300° C. for about 50 to 120 seconds. By oxidizing the silicon nitride layer, the roughness resulting from the adverse affects of amino group transport eliminated. Moreover, this high temperature step, non-plasma process can be used with the more advanced 193 nanometer technology, and is not limited to the 248 nanometer technology. A second method for exposing the silicon nitride layer to an oxidizing ambient, prior to the application of antireflective coating, introduces a mixture of N2H2 and oxygen (O2) ash at a temperature greater than or equal to 250° C. for approximately six minutes. This is followed by an O2 plasma clean and/or an Ozone clean, and then the subsequent layering of the ARC and photoresist.Type: GrantFiled: January 7, 2003Date of Patent: March 28, 2006Assignee: International Business Machines CorporationInventors: Wai-kin Li, Rajeev Malik, Joseph J. Mezzapelle
-
Patent number: 7018784Abstract: The invention relates to a process for amplifying structured resists. The process permits a subsequent increase in the etch resistance and a change in the structure size of the resist even in the case of ultrathin layers. The chemical amplification is carried out in a solvent that is so nonpolar that it does not dissolve the structured resist or dissolves it only to an insignificant extent. Because of the lower surface tension of these solvents, the danger of a collapse of these structures is additionally avoided.Type: GrantFiled: February 27, 2003Date of Patent: March 28, 2006Assignee: Infineon Technologies AGInventors: Jörg Rottstegge, Waltraud Herbst, Gertrud Falk, Eberhard Kühn
-
Patent number: 7018780Abstract: A method for controlling a removal of photoresist material from a semiconductor substrate is provided. The method includes providing the semiconductor substrate having a photoresist mask formed thereon. The method also includes forming a conformal layer of polymer over the photoresist mask and a portion of the semiconductor substrate not covered by the photoresist mask while concurrently removing a portion of the conformal layer of polymer. The thickness of the conformal layer of polymer on each region of the semiconductor substrate is set to vary depending on a removal rate of the conformal layer of polymer in each region of the semiconductor substrate.Type: GrantFiled: February 28, 2003Date of Patent: March 28, 2006Assignee: Lam Research CorporationInventors: Vahid Vahedi, Linda B. Braly
-
Patent number: 7018785Abstract: A method of forming resist patterns comprises the steps of (a) applying and forming a chemically amplified photoresist film, (b) applying a treating agent with a pH value of 1.3 to 4.5 onto said chemically amplified photoresist film, (c) baking said chemically amplified photoresist film after at least one of the steps of applying and forming said chemically amplified photoresist film and applying said treating agent, (d) selectively exposing said chemically amplified photoresist film, (e) post exposure-baking said chemically amplified photoresist film, and (f) developing said chemically amplified photoresist film, wherein the contact angle of a non-exposed portion of said chemically amplified photoresist film to a developing solution after wash with water to remove the treating agent on the photoresist and spin-drying before development is made lower by 10° to 110° than that in the case where said treating agent is not applied.Type: GrantFiled: October 24, 2001Date of Patent: March 28, 2006Assignee: AZ Electronic Materials USA Corp.Inventors: Kazuyo Ono, Yusuke Takano, Hatsuyuki Tanaka, Satoru Funato
-
Patent number: 7011934Abstract: An underlying film having pores or including an organic material is formed on a substrate. In a first chamber, hexamethyldisilazane is supplied onto the surface of the underlying film while annealing the substrate, so as to form a first molecular layer of trimethylsilyl groups on the underlying film. Thereafter, the underlying film is allowed to stand outside the first chamber. Next, in a second chamber, hexamethyldisilazane is supplied onto the surface of the first molecular layer, so as to form a second molecular layer of trimethylsilyl groups on the first molecular layer. Then, a resist film made of a chemically amplified resist material is formed above the underlying film having the second molecular layer thereon. The resist film is subjected to pattern exposure by selectively irradiating with exposing light, and the resist film is developed after the pattern exposure, so as to form a resist pattern.Type: GrantFiled: May 21, 2003Date of Patent: March 14, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masayuki Endo, Masaru Sasago
-
Patent number: 7011931Abstract: A process for forming an electrode pattern for a plasma display panel, the process including coating a photosensitive conductive paste on a film to form a pattern forming layer, laminating the film onto a substrate with the pattern forming layer facing the substrate, exposing the pattern forming layer from above the film through a mask, separating and removing the film and developing the pattern forming layer to remove unexposed areas, and firing the substrate to adhere the exposed areas of the pattern forming layer to the substrate, thus forming an electrode pattern thereon.Type: GrantFiled: November 1, 2001Date of Patent: March 14, 2006Assignee: Dai Nippon Printing, Co., Ltd.Inventors: Sakurako Hatori, Yasunori Kurima, Nobuaki Kimura, Yozo Kosaka, Satoru Kuramochi
-
Patent number: 7008754Abstract: By using a novel method, the exposure time of the photosensitive paste layer is reduced and the exposure fineness of the layer is improved, thereby developing a highly fine circuit substrate of high density having a thermal resistance at a reasonable cost. A circuit substrate is manufactured as follows. A photosensitive paste containing photoresist and a circuit material is applied onto a substrate surface so as to form a photosensitive paste layer (4). This photosensitive paste layer (4) is plotted by a laser beam (8) so as to form a plotted area (7). The photosensitive paste layer (4) is developed and an exposed area (4a) or an unexposed area (4b) is removed so as to form a circuit pattern (17). This circuit pattern (17) is sintered to form a circuit pattern (20) composed of the circuit material. It is possible to form a highly fine circuit pattern of high density by laser beam plotting.Type: GrantFiled: July 18, 2002Date of Patent: March 7, 2006Assignee: Daiken Chemical Co., Ltd.Inventors: Masatoshi Kato, Akio Harada
-
Patent number: 7008755Abstract: In a method for forming a planarized layer on a semiconductor device having concave and convex structures, a dielectric film is formed on a semiconductor substrate; a photoresist pattern is formed to have a thickness on a portion of the dielectric film other than a convex portion greater than h/n (h and n are real numbers of one or more) to remove the convex portion of the dielectric film by a depth of approximately h. The photoresist pattern is re-flowed to have a thickness below h/n at a portion from an edge of the convex portion to a slant portion of the dielectric film. The dielectric film is etched using an etchant having a selectivity of 1:n between the photoresist pattern and the dielectric film. An edge of the photoresist pattern is made thin by re-flowing thereby minimizing a pillar, hence allowing simple, fast, planarization of the dielectric film.Type: GrantFiled: June 19, 2003Date of Patent: March 7, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Jong Park, In-Seak Hwang, Tae-Won Kim
-
Patent number: 7008737Abstract: The present invention describes a method for fabricating an embossing tool or an x-ray mask tool, providing microstructures that smoothly vary in height from point-to-point in etched substrates, i.e., structure which can vary in all three dimensions. The process uses a lithographic technique to transfer an image pattern in the surface of a silicon wafer by exposing and developing the resist and then etching the silicon substrate. Importantly, the photoresist is variably exposed so that when developed some of the resist layer remains. The remaining undeveloped resist acts as an etchant barrier to the reactive plasma used to etch the silicon substrate and therefore provides the ability etch structures of variable depths.Type: GrantFiled: March 19, 2004Date of Patent: March 7, 2006Assignee: Sandia National LaboratoriesInventors: Alfredo M. Morales, Marcela Gonzales
-
Patent number: 7005245Abstract: An optical element, such as a waveguide, is formed by utilizing a plasma deposited precursor optical material wherein the plasma deposition is a two-component reaction comprising a silicon donor, which is non-carbon containing and non-oxygenated, and an organic precursor, which is non-silicon containing and non-oxygenated. The plasma deposition produces a precursor optical material that can be selectively photo-oxidized by exposure to electromagnetic energy in the presence of oxygen to produce photo-oxidized regions that have a selectively lower index of refraction than that of the non-photo-oxidized regions whereby transmission of a light signal through selected non-photo-oxidized and photo-oxidized regions can be controlled. Subsequent photo-oxidation or variable photo-oxidation can be used to produce various discrete regions with different indexes of refraction for fabrication, optimization or repair of photonic structures.Type: GrantFiled: March 4, 2002Date of Patent: February 28, 2006Inventor: Ronald M. Kubacki
-
Patent number: 7005241Abstract: A process for making a circuit board comprises the following steps of: half-etching a metal layer formed on an insulating substrate by means of a first masking which is positioned on an upper surface of the metal layer; applying a positive liquid resist on the half-etched metal layer from an upper side of the first masking; exposing the positive liquid resist with parallel light from the upper side of the first masking and developing the positive liquid resist in such a manner that a part of the positive liquid resist located under the first masking is protected to be unexposed and undeveloped; etching again the metal layer by means of a second masking composed of the first masking and the protected positive liquid resist to form a conductive pattern on the insulating substrate; and removing the first masking and the second masking from the metal layer.Type: GrantFiled: April 13, 2004Date of Patent: February 28, 2006Assignee: Shinko Electric Industries Co., Ltd.Inventors: Katsuya Fukase, Toyoaki Sakai
-
Patent number: 7001713Abstract: A method of forming a partial reverse active mask. A mask pattern comprising a large active region pattern with an original dimension and a small active region pattern is provided. The large active region pattern and the small active region pattern are shrunk until the small active region pattern disappears. The large active region pattern enlarged to a dimension slightly smaller than the original dimension.Type: GrantFiled: November 21, 2001Date of Patent: February 21, 2006Assignee: United Microelectronics, Corp.Inventors: Coming Chen, Juan-Yuan Wu, Water Lur
-
Patent number: 6998222Abstract: A method for producing an electrically conductive structure on a non-planar surface includes depositing a photosensitive resist coating onto the non-planar surface, exposing the photosensitive resist coating, removing a portion of the photosensitive resist coating, and depositing an electrically-conductive material onto portions of the non-planar surface that is substantially free of the photosensitive resist coating.Type: GrantFiled: August 17, 2001Date of Patent: February 14, 2006Assignee: Epcos AGInventors: Florian Wiest, Ignaz Eisele