Abstract: A method for patterning a carbon-containing substrate utilizing a patterned layer of a resist material as a mask and then safely removing the mask from the substrate without adversely affecting the substrate, comprising sequential steps of: (a) providing a substrate including a surface comprising carbon; (b) forming a thin metal layer on the substrate surface; (c) forming a layer of a resist material on the thin metal layer; (d) patterning the layer of resist material; (e) patterning the substrate utilizing the patterned layer of resist material as a pattern-defining mask; and (f) removing the mask utilizing the thin metal layer as a wet strippable layer or a plasma etch/ash stop layer.

Abstract: Alkaline photoresist stripping compositions containing a reducing agent to reduce or inhibit metal corrosion are disclosed. Reducing agents include compounds containing reactive multiple bonds, hydrazine and derivatives thereof, oximes, hydroquinone, pyrogallol, gallic acid and esters thereof, tocopherol, 6-hydroxy-2,5,7,8-tetramethylchroman-2-carboxylic acid, BHT, BHA, 2,6-di-tert-butyl-4-hydroxymethyl-phenol, thiols, salicylaldehyde, 4-hydroxybenzaldehyde and glycol aldehyde dialkylacetals.

Abstract: The present invention describes a method for fabricating an embossing tool or an x-ray mask tool, providing microstructures that smoothly vary in height from point-to-point in etched substrates, i.e., structure which can vary in all three dimensions. The process uses a lithographic technique to transfer an image pattern in the surface of a silicon wafer by exposing and developing the resist and then etching the silicon substrate. Importantly, the photoresist is variably exposed so that when developed some of the resist layer remains. The remaining undeveloped resist acts as an etchant barrier to the reactive plasma used to etch the silicon substrate and therefore provides the ability etch structures of variable depths.

Abstract: Antireflective compositions characterized by the presence of an SiO-containing polymer having chromophore moieties and transparent moieties are useful antireflective hardmask compositions in lithographic processes. These compositions provide outstanding optical, mechanical and etch selectivity properties while being applicable using spin-on application techniques. The compositions of the invention are advantageously useful with shorter wavelength lithographic processes and/or have minimal residual acid content.

Abstract: A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.

Abstract: A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist layer over the non-silicon containing photoresist layer; exposing an exposure surface of the silicon containing photoresist layer to an activating light source said exposure surface defined by an overlying pattern according to a photolithographic process; developing the silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least hydrogen and carbon monoxide.

Abstract: A substrate includes fine lines. The fine lines are obtained according to a fine-line forming process, which includes a process of projecting light from above the substrate onto predetermined regions on a photosensitive material provided on the substrate and a developing process after the light projection process. A narrow-width portion is provided at an end portion of each of the fine lines in a longitudinal direction of the fine line. The width of the narrow-width portion is smaller than the width of a portion adjacent to the narrow-width portion.

Abstract: It is an object to provide a manufacturing process for a printed wiring board in which a copper foil and resin as a substrate material of a copper clad laminate are irradiated with carbon dioxide gas laser light to drill in both of them simultaneously. In forming a through hole or a hole such as IVH, BVH or the like in the copper clad laminate using carbon dioxide gas laser light, one of a nickel layer of 0.08 to 2 &mgr;m in thickness, a cobalt layer of 0.05 to 3 &mgr;m in thickness and a zinc layer of 0.03 to 2 &mgr;m in thickness is formed as an additional metal layer on a surface of the copper foil residing in an external layer of the copper clad laminate and thereafter, by performing laser drilling, the copper foil layer and the resin layer as a substrate material of the copper clad laminate are enabled to drill simultaneously.

Abstract: A process is described for trimming photoresist patterns during the fabrication of integrated circuits for semiconductor devices and MEMS devices. A combination of a low temperature (<20° C.), high density oxygen and argon plasma and intense UV radiation is used to simultaneously trim and harden a photoresist linewidth in an ICP chamber. As an alternative, a UV hardening step can be performed in a flood exposure tool prior to the ICP plasma etch. Another option is to perform the argon plasma treatment first to harden the resist and then in a second step apply an oxygen plasma to trim the photoresist. Vertical and horizontal etch rates are decreased in a controllable manner which is useful for producing gate lengths in MOS transistors of less than 100 nm. The process can also be used to controllably increase a space width in a photoresist feature.

Abstract: Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic process is provided over the first anti-reflective coating, and a photosensitive material is provided above the transparent layer. The photosensitive material is exposed to a source of radiation including the wavelength of light. Preferably, the first anti-reflective coating extends beneath substantially the entire transparent layer. The complex refractive index of the first anti-reflective coating can be selected to maximize the absorption at the first anti-reflective coating to reduce notching of the photosensitive material.

Abstract: The formation of self-assembled patterns in a substrate through deformation induce by a mask placed above the substrate are disclosed. Methods of the present invention may be used to form arrays of nanometer sized pillars as well as mesas from a thin deformable layer of the substrate or a thin film of material deposited on the substrate.

Abstract: After forming first catalyst cores on the surfaces of adhesive layers of an insulating substrate, a plating resist is patterned. The insulating substrate is treated with an aqueous solution containing an anionic surfactant. Then, the insulating substrate is soaked successively in a palladium—tin mixed colloid catalyst solution and an accelerator solution, whereby second catalyst cores are formed on the surface of the adhesive layer not covered with the plating resist. Thereafter, conductive circuits are formed by electroless copper plating. Due to the anionic surfactant, adsorption of the palladium—tin mixed colloid catalyst to the plating resist is suppressed, and the first catalyst cores promote the formation of second catalyst cores. By setting the concentration of the first catalyst cores to 4×10−8 atomic mol/cm2 or less, a fine conductive circuit with a line width/line space of 50 &mgr;m or less having a high electrical insulating property between circuit lines can be formed.

Abstract: An improved method for forming a self-aligned twin well structure for use in a CMOS semiconductor device including providing a substrate for forming a twin well structure therein; forming an implant masking layer over the substrate to include a process surface said masking layer patterned to expose a first portion of the process surface for implanting ions; subjecting the first portion of the process surface to a first ion implantation process to form a first doped region included in the substrate; forming an implant blocking layer including a material that is selectively etchable to the implant masking layer over the first portion of the process surface; removing the implant masking layer to expose a second portion of the process surface; and, subjecting the second portion of the process surface to a second ion implantation process to form a second doped region disposed adjacent to the first doped region.

Abstract: One principal embodiment of the disclosure pertains to a method of optically fabricating a photomask using a direct write continuous wave laser, comprising a series of steps including: applying an organic antireflection coating over a surface of a photomask which includes a chrome-containing layer; applying a chemically-amplified DUV photoresist over the organic antireflection coating; post apply baking the DUV photoresist over a specific temperature range; exposing a surface of the DUV photoresist to the direct write continuous wave laser; and, post exposure baking the imaged DUV photoresist over a specific temperature range. The direct write continuous wave laser preferably operates at a wavelength of 244 nm or 257 nm. In an alternative embodiment, the organic antireflection coating may be applied over an inorganic antireflection coating which overlies the chrome containing layer.

Abstract: A method of forming a conductive circuit pattern on a circuit board having a first region, on which a desired conductive circuit pattern is to be formed, and a second region. The method includes the step of applying a coating including a solution with conductive particles to the circuit board. The coating is heated to adhere the conductive particles to the circuit board. The conductive particles are removed in the second region. The second region is shielded and, with the second region shielded, a conductive film is formed on the first region.

Abstract: A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed. Thereby, a trench is formed over the via hole.

Abstract: A method for generating a photoresist pattern on top of an object that includes a layer of material that is opaque to light of a predetermined wavelength. The object is first covered with a layer of photoresist material. The layer of photoresist material is then irradiated with light of the predetermined wavelength from a position under the object such that the object casts a shadow into the layer of photoresist. The photoresist material is then developed to generate the photoresist pattern. The layer of photoresist material is irradiated from below the object by providing a reflecting surface below the object and a light source above the object. A mask is positioned between the object and the light source such that the mask casts a shadow that covers the object and a portion of the area surrounding the object.

Abstract: A method of processing a substrate 30 comprises exposing the substrate 30 to an energized process gas to etch features 67 on the substrate 30 and exposing the substrate 30 to an energized cleaning gas to remove etchant residue 70 and/or remnant resist 60 from the substrate 30. To enhance the cleaning process, the substrate 30 may be treated before, during or after the cleaning process by exposing the substrate 30 to an energized treating gas comprising a halogen species.

Abstract: A resist pattern having a good form without any T-top or round top is obtained by coating on a photoresist layer an anti-reflective coating composition containing at least (a) polyacrylic acid, (b) polyvinyl pyrrolidone, (c) CnF2n+1COOOH (wherein n represents an integer of 3 to 11) and (d) tetramethylammonium hydroxide to form an anti-reflective coating, and conducting patternwise exposure and development.

Abstract: Method of forming a magnetic memory device are disclosed. In one embodiment, a first plurality of conductive lines are formed over a semiconductor workpiece. A plurality of magnetic material lines are formed over corresponding ones of the first plurality of conductive lines and a second plurality of conductive lines are formed over the semiconductor workpiece. The second plurality of conductive lines cross over the first conductive lines and the magnetic material lines. These second lines can be used as a mask to while the magnetic material lines are patterned.